2018年1月8日
A low cost and high speed CSD-based symmetric transpose block FIR implementation
Proceedings of International Conference on ASIC
- ,
- ,
- ,
- 巻
- 2017-
- 号
- 開始ページ
- 311
- 終了ページ
- 314
- 記述言語
- 英語
- 掲載種別
- 研究論文(国際会議プロシーディングス)
- DOI
- 10.1109/ASICON.2017.8252475
- 出版者・発行元
- IEEE Computer Society
In this paper, a low cost and high speed CSD-based symmetric transpose block FIR design was proposed for low cost digital signal processing. First, the existing area-efficient CSD-based multiplier was optimized by considering the reusability and the symmetry of coefficients for area reduction. Second, the position of the input register was changed for high speed transpose block FIR processing in which half of the number of required multipliers can be saved. When compared with the existing block FIR designs, the proposed FIR design can increase the data rate from 238.66 MHz to 373.13 MHz while saving 10.89% area and 21.30% energy consumption as well.
- リンク情報
- ID情報
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- DOI : 10.1109/ASICON.2017.8252475
- ISSN : 2162-755X
- ISSN : 2162-7541
- DBLP ID : conf/asicon/YeSTY17
- SCOPUS ID : 85044720982