森下 賢幸

Variable length Decoder on Dynamically Reconfigurable Cell Array Processor 

Proceedings of SPIE 4525 147-154 2001年  

Transformation From C-Program To Circuitry For a Dynamically Reconfigurable Cell Array Processor 

Proceedings of SPIE 4525 10-17 2001年  

Application of a Dynamically Reconfigurable Cell-Array Processor to an MPEG-2 Video Deader 

Proceeding of SPIE, Photonic East 2000, Massachusetts, 2000. 2000年  

A Compiler for a Dynamically Reconfigurable Processor with Cell Array Structures 

Proceeding of SPIE. Photonic East 2000, Massachusetts, 2000 2000年  

A Programming Method and a Management Unit in a Reconfigurable Processor with Cell Array Structure for General Purpose Calculation 

Proceeding of SPIE, Photonic East 2000, Massachusetts, 2000 2000年  

FPGAを用いたヤルアレイ方式ニューロプロセッサの試作 

1999年  

Implementation of Cell Array Neuro-Processor by Using FPGAs 

Proceeding of International Joint Conference on Neural Network '99 1999年  

Applications of a Connection Code Computer for Neural Network Calculations 

Proceeding of IEEE ICNN, An choradge 609-612 1998年  

Architecture of Cell Array Neuro-Processor 

Proceeding of the First International Conference on Evoluable Systems, Imnovative Architectures Session 1996年  

Processing Cell Array Neural Network MultiProcessors 

IEEE Proc. of INternational Conference Neural Network 1470 1995年  

情報処理演習・情報通信工学実験のための教育用計算機システムの構築と運用 

信学技報 ET94-100 53 1994年  

情報処理演習におけるペーパーレス化の試み 

信学技報 ET94-71 69 1994年  

Construction and Application of Computer System for Educational Environment in a Elementary Course for Information Processing and Computer and Communication Engineering Expenimentals 

TECHNICAL REPORT OF IEICE ET94-100 53 1994年  

Neural Network Multiprocessors Applied with Dynamically Reconfigurable Pipeline Architecture 

IEICE Trans. Electron E77-C(12) 1937 1994年