© 2019 IEEE. For testing delay faults in 3D IC interconnection, we have proposed a DFT (Design-for-Testability) method for TSVs using a modified boundary scan circuit with embedded Time-To-Digital Converter (TDCBS). A TDCBS cell has a delay element to form a delay line. In this paper, for improving delay resolution, delay gates that have small propagation delay time are investigated and implemented as a delay line. In order to prevent pulse shrinking of transition signal through a delay line, the proposed cell is designed to reduce the difference in transition delay between the delay for rising transition and for falling transition. The measurement results for an experimental chip show the effectiveness of our new design.