2019年10月
Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes
IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019
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- 記述言語
- 掲載種別
- 研究論文(国際会議プロシーディングス)
- DOI
- 10.1109/3DIC48104.2019.9058777
© 2019 IEEE. Dies in 3D stacked ICs are connected with Through-Silicon-Vias or micro bumps. Resistive open defects may occur at interconnects between the dies in fabrication process. The defects may grow to an open circuit fault in the field after shipping to a market. In this paper, a field test method is proposed so as the defect to be detected after shipping to a market before it becomes an open circuit fault. This test method is based on a quiescent supply current that is made flow through an interconnect between dies only in tests. It is shown by Spice simulation that an increase of 0.01Ω is detected by the test method in field tests.
- リンク情報
- ID情報
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- DOI : 10.1109/3DIC48104.2019.9058777
- SCOPUS ID : 85084108412