2019年1月4日
Resistive open defect detection in SoCs by a test method based on injected charge volume after test input application
2018 IEEE CPMT Symposium Japan, ICSJ 2018
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- 開始ページ
- 141
- 終了ページ
- 142
- 記述言語
- 掲載種別
- 研究論文(国際会議プロシーディングス)
- DOI
- 10.1109/ICSJ.2018.8602818
© 2018 IEEE. A test method is proposed of resistive open defects in an SoC by means of charge volume injected from the VDD terminal. The charge is injected after providing a test input vector from a charge injector instead of a DC power voltage source. It is shown by Spice simulation that a resistive open defect in four parallel inverter chain circuits of 30 stages whose resistance is larger than 10k Ω can be detected by the test method.
- リンク情報
- ID情報
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- DOI : 10.1109/ICSJ.2018.8602818
- SCOPUS ID : 85061740936