2018年12月6日
Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design
Proceedings of the Asian Test Symposium
- ,
- ,
- 巻
- 2018-October
- 号
- 開始ページ
- 7
- 終了ページ
- 12
- 記述言語
- 掲載種別
- 研究論文(国際会議プロシーディングス)
- DOI
- 10.1109/ATS.2018.00013
© 2018 IEEE. A boundary scan design with embedded time-to-digital converter (TDCBS) has been proposed for testing small delay faults. In this paper, the TDCBS is applied for testing TSVs in 3D IC. To reduce test application time of the TDCBS, we propose a modified TAP controller that utilizes the bypass mode for reducing unnecessary scan shifts during observation of the captured results. The simulation for an experimental circuit is shown to evaluate the effectiveness of the proposed method.
- リンク情報
- ID情報
-
- DOI : 10.1109/ATS.2018.00013
- ISSN : 1081-7735
- SCOPUS ID : 85060031897