小野美 武

High-speed single flux quantum parallel multiplier using Dadda type partial product addition 

7th International WorkShop on New Group IV Semiconductor Nanoelectronics and JSPS Core-to-Core Program Joint Seminar "Atomically Controlled Processing for Ultralarge Scale Integration" :P-16 2014年1月  

Characteristics of rf-SQUID Ladder Circuits 

Proceedings of Superconducting SFQ VLSI Workshop SSV 2013 60-63 2013年11月  

Comparative Study of SFQ Parallel Multipliers 

Proceedings of Superconducting SFQ VLSI Workshop SSV 2013 78-81 2013年11月  

An improved superconducting neural circuit and its application for a neural network solving a combinatorial optimization problem 

8th European Conf. on Applied Superconductivity 3P-EL1-16 2013年9月  

Design and Fabrication of an Improved Neural Circuit for Superconducting Neural Network Solving a Combinatorial Optimization Problem 

Proceedings of Superconducting SFQ VLSI Workshop SSV 2012 63-66 2012年12月  

High Throughput Parallel Arithmetic Circuits for Fast Fourier Transform 

IEICE TRANSACTIONS ON ELECTRONICS E94C(3) 280-287 2011年3月  

High Throughput Parallel Multiplier of SFQ Circuits based on the Booth Encoder 

The 3rd Student Organizing International Mini-Conference on Information Electronics Systems 172-173 2010年10月