Kazuhiro Nakamura - My portal

Profile Information

Affiliation: Faculty of Engineering Department of Computer and Information Engineering, Nippon Institute of Technology

Degree: Doctor of Engineering(Nara Institute of Science and Technology)

Researcher number: 90335076
J-GLOBAL ID: 200901053723086137
researchmap Member ID: 1000253252

Research Areas

Research History

2018 - Present

Faculty of Advanced Engineering, Department of Information Technology and Media Design, Nippon Institute of Technology
2013 - 2018

Nippon Institute of Technology
2006 - 2013

Assistant Professor, Nagoya University Graduate School of Information Science, Granduate School of Information Science Center for Embedded Computing Systems
2004 - 2006

Graduate School of Information Science, Graduate School of Information Science, Nagoya University
2001 - 2003

Center for Information Media Studies, Nagoya University

Education

Awards

2000

第 2 回 LSI IP デザインアワード IP 賞

Papers

初年次プログラミング科目におけるTA/SAの知識継承と教育力向上の試み

大橋裕太郎, 勝間田仁, 中村一博, 橋浦弘明, 松浦隆文, 石原次郎, 山地秀美

工学教育, 67(1) 26-31, Jan, 2019 Peer-reviewed
Comparison of educational video production methods for students studying computer programming

Yutaro Ohashi, Masashi Katsumata, Kazuhiro Nakamura, Hiroaki Hashiura, Takafumi Matsuura, Jiro Ishihara, Hidemi Yamachi, Fumihiro Kumeno, Yasuhiro Tsujimura

ACM International Conference Proceeding Series, Part F148391 105-110, Jan, 2019 Peer-reviewed
Knowledge Sharing and Teaching Ability Improvement of Teaching Assistants and Student Assistants in a First-Year Computer Programming Course

Yutaro OHASHI, Masashi KATSUMATA, Kazuhiro NAKAMURA, Hiroaki HASHIURA, Takafumi MATSUURA, Jiro ISHIHARA, Hidemi YAMACHI

Journal of JSEE, 67(1) 54-59, Jan, 2019 Peer-reviewed
Practice and Analysis of PBL Class for 3rd Grade Undergraduate Students

Nakamura Kazuhiro, Kato Toshiyasu, Katsumata Masashi, Takase Hiroshi, Niwa Jiro

IEEJ Transactions on Electronics, Information and Systems, 138(7) 877-885, Jul, 2018 Peer-reviewed
Practices of Self-paced Learning with Prior Learning Materials and Exercises in First-year Programming Courses

KATSUMATA Masashi, OHASHI Yutaro, NAKAMURA Kazuhiro, HASHIURA Hiroaki, MATSUURA Takafumi, ISHIHARA Jiro, YAMACHI Hidemi

Journal of JSEE, 65(5) 42-47, Oct, 2017 Peer-reviewed
A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition

Kazuhiro Nakamura, Ryo Shimazaki, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi

IEICE TRANSACTIONS ON ELECTRONICS, E95C(4) 456-467, Apr, 2012 Peer-reviewed
A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing

Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E93D(2) 300-305, Feb, 2010 Peer-reviewed
Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems

Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi

Proceedings - IEEE International Symposium on Circuits and Systems, 1688-1691, 2008 Peer-reviewed
実時間システムのための近似手法に基づいた記号モデル検査器の開発と評価

山根智, 中村一博

電子情報通信学会論文誌 D-I, J86-D-I(4) 232-247, 2003 Peer-reviewed
Multi-cycle path detection based on propositional satisfiability with CNF simplification using adaptive variable insertion

K Nakamura, S Maruoka, S Kimura, K Watanabe

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E83A(12) 2600-2607, Dec, 2000 Peer-reviewed
Timing verification of sequential logic circuits based on controlled multi-clock path analysis

K Nakamura, S Kimura, K Takagi, K Watanabe

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E81A(12) 2515-2520, Dec, 1998

Misc.

Practice of Online Class "Programming I" using Teams

50(3) 7-9, Feb, 2021
大学の一般教育としてのプログラミング教育における到達目標の検討

加藤利康, 勝間田仁, 中村一博

情報処理学会第82回全国大会, 5H-07 311-312, Mar, 2020
プログラミング教育必修化世代を対象としたプログラミング理解度判定テストの構築

勝間田仁, 加藤利康, 中村一博

情報処理学会第82回全国大会, 5H-02 301-302, Mar, 2020
学部PBL型授業における同一テーマ複数チームの活動報告書に対するテキスト分析と考察

加藤利康, 中村一博, 勝間田仁, 高瀬浩史

第17回情報科学技術フォーラム, Sep, 2018
An Efficient Binary Comparator Design Method for Strip-Mining and Loop-Tiling

Naoaki Shibata, Hiroto Kondo, Hiiro Miyai, Kazuhiro Nakamura

第31回回路とシステムワークショップ, May, 2018 Peer-reviewed
Sharing Knowledge and Improving Teaching Ability of Teaching Assistants and Student Assistants in Computer Programming Classes

大橋裕太郎, 勝間田仁, 中村一博, 橋浦弘明, 松浦隆文, 石原次郎, 山地秀美

情報処理学会研究報告(Web), 2017(CE-140) Vol.2017‐CE‐140,No.8,1‐7 (WEB ONLY), Jul 1, 2017
工科系大学での初年次プログラミング教育におけるTA/SA評価のためのルーブリックの開発

大橋裕太郎, 勝間田仁, 中村一博, 石原次郎, 橋浦弘明, 松浦隆文, 山地秀美

情報処理学会研究報告(Web), 2016(CE-136) Vol.2016‐CE‐136,No.12,1‐4 (WEB ONLY), Oct 8, 2016
学部3年通年必修PBL型授業の設計と実践

中村一博, 加藤利康, 勝間田仁, 高瀬浩史, 丹羽次郎

情報科学技術フォーラム講演論文集, 15th 435‐436, Aug 23, 2016
Supplemental information on sequential circuits for accelerating verification and improving bit-width estimation accuracy (2)(Researches)

Kazuhiro Nakamura

45(4) 50-51, Feb, 2016
Memory efficient VLSI architecture of output probability and likelihood score computations for HMM-based word recognition using multiple fast store-based block parallel processing

IEICE technical report, 110(473) 225-230, Mar 18, 2011
Memory Efficient VLSI Architecture of Output Probability and Likelihood Score Computations for HMM-based Word Recognition Using Multiple Fast Store-based Block Parallel Processing

2011(38) 1-6, Mar 11, 2011
Acceralation of Bounded Model Checking for Sequential Circuits with Two-phase Verification

ONO Norihiro, NAKAMURA Kazuhiro, TAKAGI Kazuyoshi, TAKAGI Naofumi

IEICE technical report, 110(432) 159-164, Feb 23, 2011
Memory efficient pixel-parallel Hough transform circuit using collision-at-most-one and localized voting space access

IEICE technical report, 110(316) 85-90, Nov 29, 2010
Memory efficient pixel-parallel Hough transform circuit using collision-at-most-one and localized voting space access

IEICE technical report, 110(317) 85-90, Nov 29, 2010
Memory Efficient Pixel-parallel Hough Transform Circuit Using Collision-at-most-one and Localized Voting Space Access

2010(16) 1-6, Nov 22, 2010
A Fast VLSI Architecture of Output Probability Computations and Viterbi Scorer for HMM-Based Recognition Systems with Store-Based Block Parallel Processing

SHIMAZAKI RYO, NAKAMURA KAZUHIRO, YAMAMOTO MASATOSHI, TAKAGI KAZUYOSHI, TAKAGI NAOFUMI

2010(8) 1-8, Mar 19, 2010
Estimating Signal Transition Frequency of Arithmetic Circuits Using Cell Delay Model

KAWASHIMA Hirotaka, NAKAMURA Kazuhiro, TAKAGI Kazuyoshi, TAKAGI Naofumi

IEICE technical report, 109(462) 151-156, Mar 3, 2010
Circuit conversion for reducing false negatives on formal verification of sequential circuit

ONO Norihiro, NAKAMURA Kazuhiro, TAKAGI Kazuyoshi, TAKAGI Naofumi

IEICE technical report, 109(462) 157-162, Mar 3, 2010
A-3-1 Multi Time-frame State Reduction for Sequential SAT with m-Trie

TORII Kousuke, NAKAMURA Kazuhiro, TAKAGI Kazuyoshi, TAKAGI Naofumi

Proceedings of the IEICE General Conference, 2010 70-70, Mar 2, 2010
Memory Efficient Pipelined TLDP Architecture for Connected Word Speech Recogntion

SHIMAZAKI RYO, NAKAMURA KAZUHIRO, TAKAGI KAZUYOSHI, TAKAGI NAOFUMI

2010(11) 1-6, Jan 21, 2010

Presentations

学部3年通年必修PBL型授業の実践と分析

中村一博, 加藤利康, 勝間田仁, 高瀬浩史, 丹羽次郎

電気学会電子・情報・システム部門大会, 2017
学部3年通年必修PBL型授業の設計と実践

中村一博, 加藤利康, 勝間田仁, 高瀬浩史, 丹羽次郎

第15回情報科学技術フォーラム, 2016

Professional Memberships

Research Projects

Research on synthesis of easily-testable arithmetic circuits

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, 2008 - 2010

TAKAGI Naofumi, TAKAGI Kazuyoshi, NAKAMURA Kazuhiro
論理回路の形式的検証の正確さ向上に関する研究

若手研究（B）, 科学研究費助成事業, 2008 - 2009

中村一博
順序回路のタイミング解析の正確さ向上に関する研究

若手研究（B）, 科学研究費助成事業, 2006 - 2007

中村一博
携帯機器向けＨＭＭベース音声・映像認識ＬＳＩのための認識エンジン自動生成の研究

若手研究（B）, 科学研究費助成事業, 2003 - 2004

中村一博
Researches on hardware algorithms for arithmetic operations in finite fields.

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, 2002 - 2004

TAKAGI Naofumi, TAKAGI Kazuyoshi, NAKAMURA Kazuhiro, NISHINAGA Nozomu
VLSI CAD Algorithm

1999