Jan 6, 2006
Characteristics improvement of PLLs using phase interpolation : Circuit optimization of phase interpolation
IEICE technical report
- ,
- ,
- Volume
- 105
- Number
- 504
- First page
- 13
- Last page
- 17
- Language
- Japanese
- Publishing type
- Publisher
- The Institute of Electronics, Information and Communication Engineers
Normal PLL (Phase Locked Loop) compares phases of reference and input at the time of their positive transition. We propose a new PLL using phase interpolation based on a counter with a high-frequency internal clock. The PLL can compare phases more than once a cycle of reference and input, thus reducing jitter and improving resonsiveness. Also we optimize implementation of phase interpolation, to improve circuit size and maximum operating frequency, even if the circuit compares phases many time a cycle.
- Link information
-
- CiNii Articles
- http://ci.nii.ac.jp/naid/110004082729
- CiNii Books
- http://ci.nii.ac.jp/ncid/AN10013094
- URL
- http://id.ndl.go.jp/bib/7813632
- ID information
-
- ISSN : 0913-5685
- CiNii Articles ID : 110004082729
- CiNii Books ID : AN10013094