Normal PLL (Phase Locked Loop) compares phases of reference and input at the time of their positive transition. We propose a new PLL using phase interpolation based on a counter with a high-frequency internal clock. The PLL can compare phases more than once a cycle of reference and input, thus reducing jitter and improving responsiveness. Also we optimize implementation of phase interpolation, to improve circuit size and maximum operating frequency, even if the circuit compares phases many time a cycle.