Recently, radiation-hardened optically reconfigurable gate arrays have been developed for space applications. An optically reconfigurable gate array comprises a holographic memory, a laser array, and an optically reconfigurable gate array VLSI. Since the optically reconfigurable gate array is a type of multi-context field programmable gate array (FPGA), several configuration contexts must be implemented onto the holographic memory on an optically reconfigurable gate array. However, the holographic memory pattern calculation is a heavy operation in addition to logic synthesis and to place and route operations. This paper therefore presents an FPGA hardware accelerator for hologram memory calculation for optically reconfigurable gate arrays with an FPGA (Cyclone V
Altera Corp.).Performance evaluation results show that the calculation speed of a hologram memory pattern including 512 bright bits is 16.9 times higher than multi-thread calculation on the CPU (Core i7-4770
Intel Corp.). Furthermore, the FPGA hardware accelerator power consumption is only 6 W, compared to 95 W of the CPU (Core i7-4770
Intel Corp.).