論文

査読有り
2017年1月

Optically reconfigurable gate array platform for Mono-instruction set computer architecture

2017 IEEE 7th Annual Computing and Communication Workshop and Conference
  • Hiroki Shimba
  • ,
  • Minoru Watanabe

開始ページ
1
終了ページ
4
記述言語
英語
掲載種別
研究論文(国際会議プロシーディングス)
DOI
10.1109/CCWC.2017.7868473
出版者・発行元
IEEE

The operating clock frequency of the latest processor has never been increased because of recent process issues. A game change must occur to achieve progress in clock frequencies. Therefore, we propose a mono-instruction set computer (MISC) architecture based on optically reconfigurable gate array architecture. The MISC architecture consists of various single instruction processor cores having only one instruction. Using the MISC architecture, the processor performance can be increased drastically. However, the only requirement is the use of a highspeed dynamically reconfigurable device or an optically reconfigurable gate array (ORGA). As described herein, we present the latest ORGA and discuss benefits of MISC architecture based on the ORGA.

リンク情報
DOI
https://doi.org/10.1109/CCWC.2017.7868473
Web of Science
https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:000403388800136&DestApp=WOS_CPL
URL
https://ieeexplore.ieee.org/document/7868473
ID情報
  • DOI : 10.1109/CCWC.2017.7868473
  • Web of Science ID : WOS:000403388800136

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