To date, optically reconfigurable gate arrays (ORGAs) have been developed to address high-speed operations. During that development, a MEMS dynamic optically reconfigurable gate array architecture was proposed: it perfectly removes the static configuration memory to store a context and uses junction capacitances of photodiodes as dynamic configuration memory to realize high-gate count ORGA-VLSI. However, this architecture presents the issue that retention time of programmed circuits on a gate array is, just like DRAMs, not infinite. Since the circuit reconfiguration frequency is always superior to the refresh cycle frequency, the refresh cycle problem need not be considered. However, circuits with a long lifetime exist among the many implementation circuits. For these circuits, many refresh cycles must be required continuously. Therefore, This paper presents a proposal of a retention time improvement method by adjusting the threshold level in the holographic memory calculation. ©2010 IEEE.