Dynamic reconfigurable devices present new computational paradigms because programmable devices' activity and performance can be improved dramatically merely by increasing the reconfiguration frequency. Therefore, the reconfiguration time and reconfiguration overhead of next-generation programmable devices are extremely important parameters. To realize zero-overhead and short reconfiguration, an Optically Differential Reconfigurable Gate Array (ODRGA) VLSIs were developed. However, up to now, the scaling rule of ODRGAs has never been clarified. This paper describes the designs of ODRGA-VLSIs using 0.18 mu m and 0.35 mu m CMOS processes and presents discussion of the scaling rule of ODRGAs using layout results.