2004
Sampling rate conversion by Fourier interpolation
SICE 2004 ANNUAL CONFERENCE, VOLS 1-3
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- First page
- 1613
- Last page
- 1616
- Language
- English
- Publishing type
- Research paper (international conference proceedings)
- Publisher
- SOC INSTRUMENT CONTROL ENGINEERS JAPAN
New time-domain SRC using Fourier interpolation to achieve less gate count than in frequency domain is proposed and implemented by FPGA. Layout area of the proposed SRC based on a 0.35 mu m process is 5.728mm(2), smaller than the conventional SRC using filters. The noise level is reduced down to the quantizaion error level by using several improving methods.
- Link information
- ID information
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- Web of Science ID : WOS:000231324801134