村上 和彰

Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs(共著) 

IEICE Trans. on Information and Systems E83-D(5) 1048-1057 2000年  

A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection(共著) 

IEICE Trans. on Electronics E83-C(2) 186-194 2000年  

MOE : A Special-Purpose Parallel Computer for High-Speed, Large Scale Molecular Orbital Calculation(共著) 

Proc. of 1999 Supercomputing(SC99) 1999年  

Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs(共著) 

Proc. of the IEEE 5th International Symposium on High-Performance Computer Architecture(HPCA-5) 218-222 1999年  

Evaluating DRAM Refresh Architectures for Merged DRAM/Logic LSIs(共著) 

IEICE Trans. on Electronics E81-C(9) 1455-1462 1998年  

Analyzing and Reducing the Impact of Shorter Data Retention Time on the Performance of Merged DRAM/Logic LSIs(共著) 

IEICE Trans. on Electronics E81-C(9) 1448-1454 1998年  

High Bandwidth, Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs(共著) 

IEICE Trans. on Electronics E81-C(9) 1438-1447 1998年  

Parallel Processing RAM Chip with 256Mb DRAM and Quad Processors(共著) 

Digest of Technical Papers, 1997 IEEE International Solid-State Circuits Conference FP14.3 FP14.3 1997年