1999年6月
Two-dimensional cyclic bias device simulator and its application to GaAsHJFET pulse pattern effect analysis
IEICE TRANSACTIONS ON ELECTRONICS
- ,
- ,
- 巻
- E82C
- 号
- 6
- 開始ページ
- 917
- 終了ページ
- 923
- 記述言語
- 英語
- 掲載種別
- 出版者・発行元
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
A device simulator that simulates device performance in the cyclic bias steady state was del eloped. and it was applied to GaAs hetero-junction FET (HJFET) pulse pattern effect. Although there is a large time-constant difference between the pulse signals and deep trap reactions, the simulator searches the cyclic bias steady states at about 30 iterations. A non-linear shift in the drain current level with the mark ratio was confirmed. which has been estimated from the rate equation of electron capture and emission based on Shockley-Read-Hall statistics fur deep traps.
- リンク情報
- ID情報
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- ISSN : 0916-8524
- eISSN : 1745-1353
- Web of Science ID : WOS:000081211400016