宮下弘 (Hiroshi Miyashita) - マイポータル

基本情報

Thermal-aware placement based on FM partition scheme and force-directed heuristic

J Li, H Miyashita

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E89A(4) 989 - 995 2006年4月
An incremental placement algorithm for building block layout design based on the O-tree representation

J Li, JB Yu, H Miyashita

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E88A(12) 3398 - 3404 2005年12月
Equidistance routing in high-speed VLSI layout design

Y Kubo, H Miyashita, Y Kajitani, K Tateishi

INTEGRATION-THE VLSI JOURNAL 38(3) 439 - 449 2005年1月
Equidistance routing in high-speed VLSI layout design

Y Kubo, H Miyashita, Y Kajitani, K Tateishi

INTEGRATION-THE VLSI JOURNAL 38(3) 439 - 449 2005年1月
Dimension of partial orders and its application to rectangle packing(共著)

Research Institute for Mathematical Sciences Kokyuroku 1340, pp.65-76 2003年

Efficient thermal via planning for placement of 3D integrated circuits

2007 IEEE International Symposium on Circuits and Systems 2007年
Thermal-aware placement using Lagrangian relaxation combined with a partition scheme

2006 International Conf. on Communications, Circuits and Systems 2006年
Post-placement thermal via planning for 3D integrated circuits

The 2006 IEEE Asia Pacific Conference on Circuits and Systems 2006年
Thermal-aware placement based on FM partition scheme and force-directed heuristic

The 18th Workshop on Circuits and Systems in Karuizawa 2005年
Stochastic equi-length channel routing with channel height minimization

The 20th Commemorative International Technical Conference on Cirsuits/Systems, Computers and Communications (ITC-CSCC 2005) 2005年