宮下弘 (Hiroshi Miyashita) - マイポータル

基本情報

所属: 北九州市立大学国際環境工学部情報メディア工学科北九州市立大学国際環境工学部情報メディア工学科 (大学院国際環境工学研究科情報工学専攻) 教授

学位: 理学修士(東京工業大学)
博士(工学)(東京工業大学)

J-GLOBAL ID: 200901056282630609
researchmap会員ID: 1000364122

研究キーワード

研究分野

MISC

Thermal-aware placement based on FM partition scheme and force-directed heuristic

J Li, H Miyashita

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E89A(4) 989-995 2006年4月
An incremental placement algorithm for building block layout design based on the O-tree representation

J Li, JB Yu, H Miyashita

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E88A(12) 3398-3404 2005年12月
Equidistance routing in high-speed VLSI layout design

Y Kubo, H Miyashita, Y Kajitani, K Tateishi

INTEGRATION-THE VLSI JOURNAL 38(3) 439-449 2005年1月
Dimension of partial orders and its application to rectangle packing(共著)

Research Institute for Mathematical Sciences Kokyuroku 1340, pp.65-76 2003年
Dimension of partial orders and its application to rectangle packing(共著)

Research Institue for Mathematical Sciences Kokyuroku 1340, pp.65-76 2003年
On the equivalence of the sequence pair for rectangle packing to the dimension of partial orders

Proc. of the 2002 IEEE Asia Pacific Conference on Circuits and Systems 2002年
Extending pitchmatching algorithms to layouts with multiple grid constraints

H Miyashita

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E79A(6) 900-909 1996年6月
PROCEDURAL DETAILED COMPACTION FOR THE SYMBOLIC LAYOUT DESIGN OF CMOS LEAF-CELLS

H MIYASHITA

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E77A(11) 1957-1969 1994年11月
A preconstrained compaction method applied to direct design-rule conversion of CMOS layouts

IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences E77-A(10) 1684-1692 1994年
An automated approach to generating leaf cells for a macro cell configuration(共著)

IEICE Transactions on Fundamentals of Electronics, Communications and computer Sciences E76-A(8) 1334-1342 1993年
Probabilistic methods in VLSI layout design(共著)

Proc. of the 11th Symposium on Applied Functional Analysis-Information Theory and Related Topics 129-140 1988年
Probalistic compaction algorithm for LSI cell layout design(共著)

Electronics Letters 23(8) 408-410 1987年
An automatic cell pattern generation system for CMOS transistor-pair array LSI(共著)

Integration, the VLSI journal 4(2) 115-133 1986年
CMOSマスタスライスLSIのセルパタン自動生成(共著)

電子通信学会論文誌 J66-C(12) 1140-1147 1983年
Cell pattern generation for CMOS masterslice LSI

Transactions on the Institute of Electronics and Communication Engineers J66-C(12) 1140-1147 1983年

書籍等出版物

数理情報科学事典(共著)

朝倉書店 1995年

講演・口頭発表等

Efficient thermal via planning for placement of 3D integrated circuits

2007 IEEE International Symposium on Circuits and Systems 2007年
Thermal-aware placement using Lagrangian relaxation combined with a partition scheme

2006 International Conf. on Communications, Circuits and Systems 2006年
Post-placement thermal via planning for 3D integrated circuits

The 2006 IEEE Asia Pacific Conference on Circuits and Systems 2006年
Thermal-aware placement based on FM partition scheme and force-directed heuristic

The 18th Workshop on Circuits and Systems in Karuizawa 2005年
Stochastic equi-length channel routing with channel height minimization

The 20th Commemorative International Technical Conference on Cirsuits/Systems, Computers and Communications (ITC-CSCC 2005) 2005年
Equidistance routing in high-speed VLSI layout design

Proc. of the 2004 ACM Great Lakes Symposium on VLSI 2004年
An incremental placement algorithm for building block layout design based on the O_tree non-slicing representation

2004 International Conference on Communications, Circuits and Systems 2004年
On the equivalence of the sequence pair for rectangle packing to the dimension of partial orders

2002 IEEE Asia-Pacific Conference on Circuits and Systems 2002年
Extending pitchmatching algorithm to layouts with multiple grid constraints

Proc. of Asia and South-Pacific Design Automation Conference 1995年
Use of preconstrained compaction for direct design-rule conversion of CMOS cells

The 1992 IEEE Asia Pacific Conference on Circuits and Systems 1992年
An experimental comparison of simulated annealing and conventional placement methods

Joint Technical Conference on Circuits/Systems, Computers and Communications 1988年
An automatic cell pattern generation system for CMOS pair-transistor array LSI

Proc. of VLSI'85 - International Conference on Very Large Scale Integration 1985年

宮下弘

基本情報

研究キーワード

研究分野

MISC

書籍等出版物

講演・口頭発表等

所属学協会

共同研究・競争的資金等の研究課題

産業財産権

メニュー