中村広記 (Hiroki Nakamura) - マイポータル - researchmap

基本情報

所属: 旧所属東北大学電気通信研究所情報デバイス研究部門助手

J-GLOBAL ID: 200901094363741900
researchmap会員ID: 1000365474

MISC

55

A novel tri-control gate surrounding gate transistor(TCG-SGT) nonvolatile memory cell for flash memory

Takuya Ohba, Hiroki Nakamura, Hiroshi Sakuraba, Fujio Masuoka

SOLID-STATE ELECTRONICS 50(6) 924-928 2006年6月
Decananometer surrounding gate transistor (SGT) scalability by using an intrinsically-doped body and gate work function engineering

Y Yamamoto, T Hidaka, H Nakamura, H Sakuraba, F Masuoka

IEICE TRANSACTIONS ON ELECTRONICS E89C(4) 560-567 2006年4月
The new Shielded Bitline Sensing Method for FC-SGT Flash memory

64th Device Research Conference Digest ,57-58 2006年
Fabrication Process of Floating Channel Type Surrounding Gate Transistor Flash Memory on an SOI Substrate

Proceesings of the 5th International Conference on Semiconductor Technology (ISTC2006) ,116-120 2006年
Dependence of Coupling Ratio of High Capacitive-Coupling Ratio Surrounding Gate Transistor (HiCR-SGT) Flash Memory Cell on Structural Parameters

210th Meeting of The Electrochemical Society Meeting Abstracts ,Abstract.30 2006年
Analysis of the ID-VG Characteristics of the Concave Diffusion Layer Type Surrounding Gate Transistor (CC-SGT) with 20nm Silicon Pillar for Suppressing Substrate Bias Effect

Proceesings of the 5th International Conference on Semiconductor Technology (ISTC2006) ,201-207 2006年
Novel High Capacitive-Coupling Ratio Surrounding Gate Transistor (HICR-SGT) Flash Memory Cell with a Step-Like Silicon Pillar Structure

Proceesings of the 5th International Conference on Semiconductor Technology (ISTC2006) ,121-125 2006年
Silicon Pillar Fabricated for SGT with varying the content of O2 in Cl2/O2 gases by Using ECR plasma etching

210th Meeting of The Electrochemical Society Meeting Abstracts ,Abstract.987 2006年
フィードバック技術を用いた新しいビットラインダイレクトセンス回路によるフラッシュメモリの高速化

電子情報通信学会論文誌C J89-C(1) 40-47 2006年
The new Shielded Bitline Sensing Method for FC-SGT Flash memory

64th Device Research Conference Digest ,57-58 2006年
Fabrication Process of Floating Channel Type Surrounding Gate Transistor Flash Memory on an SOI Substrate

Proceesings of the 5th International Conference on Semiconductor Technology (ISTC2006) ,116-120 2006年
Dependence of Coupling Ratio of High Capacitive-Coupling Ratio Surrounding Gate Transistor (HiCR-SGT) Flash Memory Cell on Structural Parameters

210th Meeting of The Electrochemical Society Meeting Abstracts ,Abstract.30 2006年
Analysis of the ID-VG Characteristics of the Concave Diffusion Layer Type Surrounding Gate Transistor (CC-SGT) with 20nm Silicon Pillar for Suppressing Substrate Bias Effect

Proceesings of the 5th International Conference on Semiconductor Technology (ISTC2006) ,201-207 2006年
Novel High Capacitive-Coupling Ratio Surrounding Gate Transistor (HICR-SGT) Flash Memory Cell with a Step-Like Silicon Pillar Structure

Proceesings of the 5th International Conference on Semiconductor Technology (ISTC2006) ,121-125 2006年
Silicon Pillar Fabricated for SGT with varying the content of O2 in Cl2/O2 gases by Using ECR plasma etching

210th Meeting of The Electrochemical Society Meeting Abstracts ,Abstract.987 2006年
Analysis of the subthreshold characteristics for the FC-SGT flash memory cell

Hiroaki Yamazaki, Hiroki Nakamura, Hiroshi Sakuraba, Fujio Masuoka

ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS 89(8) 34-41 2006年
A novel bit-line direct-sense circuit that uses a feedback system for high-speed flash memory

Takuya Kadowaki, Hiroki Nakamura, Hiroshi Sakuraba, Fujio Masuoka

ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS 89(8) 1-8 2006年
Fabrication of nanometer silicon pillars for buried-gate-type surrounding gate transistor by silicon quasi-isotropic etching

T Kitagawa, T Hidaka, T Ohba, H Amikawa, T Izumida, S Ohtsu, H Nakamura, H Sakuraba, F Masuoka

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 45(1A) 54-56 2006年1月
NAND-type DRAM-on-SGT

H Nakamura, H Sakuraba, F Masuoka

IEEE TRANSACTIONS ON ELECTRON DEVICES 52(3) 427-429 2005年3月
NAND-type DRAM-on-SGT

Hiroki Nakamura, Hiroshi Sakuraba, Fujio Masuoka

IEEE Transactions on Electron Devices 52(3) 427-429 2005年3月

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