2008年
Parallel implementation of DPCM decoding for SMP systems
SERA 2008: 6TH ACIS INTERNATIONAL CONFERENCE ON SOFTWARE ENGINEERING RESEARCH, MANAGEMENT AND APPLICATIONS, PROCEEDINGS
- 開始ページ
- 69
- 終了ページ
- 74
- 記述言語
- 英語
- 掲載種別
- DOI
- 10.1109/SEPA.2008.13
- 出版者・発行元
- IEEE COMPUTER SOC
DPCM (Differential Pulse Code Modulation) coding is widely used in many applications including lossless JPEG compression. DPCM decoding is inherently a 1-indexed or 2-indexed recurrence relation. Thus, although it is hard to parallelize efficiently, some (N log N)or (log(2) N) algorithms have been studied for an N x N image with N x N or N processors. Recently commodity microprocessors are equipped with plural cores and SMP architectures are utilized in some PCs, but the number of parallelism is not so large (up to 80). Thus, it is unrealistic that the image processing of an N x N image is parallelized with N x N or N processors. In this paper we implements two parallel DPCM algorithms for an N x N image on P processors (P << N): Fat-pipeline and P-scheme. Our experimental results show that both approaches provide the parallelisms of about 3.2 with 6 processing cores.
- リンク情報
- ID情報
-
- DOI : 10.1109/SEPA.2008.13
- Web of Science ID : WOS:000259298900010