NAKAMURA Kazuyuki

J-GLOBAL         Last updated: Nov 22, 2018 at 03:11
 
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Name
NAKAMURA Kazuyuki
URL
http://www.design.cms.kyutech.ac.jp/~nakamura/
Affiliation
Kyushu Institute of Technology
Section
Center for Microelectronic Systems
Job title
Professor,Director
Degree
Doctor of Engineering(Kyushu University)
Other affiliation
Kyushu Institute of TechnologyKyushu Institute of Technology

Research Areas

 
 

Academic & Professional Experience

 
2006
   
 
 Professor,Center for Microelectronic Systems,Kyushu Institute of Technology
 
2014
 - 
2018
 Vice Director,Center for Microelectronic Systems,Kyushu Institute of Technology
 
2018
   
 
 Director,Center for Microelectronic Systems,Kyushu Institute of Technology
 
2008
   
 
 Professor,Department of Creative Informatics,Graduate School of Computer Science and Systems Engineering,Kyushu Institute of Technology
 
2013
   
 
 Professor,Research Center for Dependable Integrated Systems,Kyushu Institute of Technology
 

Education

 
 
 - 
1988
Graduate School, Division of Engineering, Kyushu University
 
 
 - 
1986
Department of Electrical Engineering, Faculty of Engineering, Kyushu University
 

Misc

 
K. Matsuyama,K. Nakamura,H. Asada,T. Suzuki,K. Fujimoto,and S. Konishi
Journal of Applied Physics   63(8) 3171-3173   1988
A 5ns 1Mb ECL BiCMOS SRAM
M.Takada,K.Nakamura,T.Takeshima,K.Furuta,T.Yamazaki,K.Imai,S.Ohi,Y.Fukuda,Y.Minato and H.Kimoto
1990 ISSCC Digest of Technical Papers   138-139   1990
A 5ns 1Mb BiCMOS SRAM with ECL Interface
M.Takada,K.Nakamura,T.Takeshima,K.Furuta,T.Yamazaki,K.Imai,S.Ohi,Y.Fukuda,Y.Minato and H.Kimoto
1990 ISCAS      1990
M.Takada,K.Nakamura,T.Takeshima,K.Furuta,T.Yamazaki,K.Imai,S.Ohi,Y.Sekine,Y.Minato and H.Kimoto
IEEE Journal of Solid-State Circuits   25 1057-1062   1990
Logic Functional Level Converter for High Speed Address Decoder of ECL I/O BiCMOS SRAMs
K.Nakamura,M.Takada,T.Takeshima,K.Furuta,T.Yamazaki,K.Imai,S.Ohi,Y.Sekine,Y.Minato and H.Kimoto
IEICE Transactions on Electronics   E74(4)    1991

Conference Activities & Talks

 
Realization of Multiple-output functions by sequential Look-up Table Cascades
2004   
A Study on CMOS Even-Stage Ring Oscillators Containing Plural Latches
2009   
A Study on CMOS Even-Stage Ring Oscillators Containing Single-channel Latches
2010   
Study on Oscillation Condition for Even-Stage Ring Oscillators with Supply-voltage Transition
2011   
A Measurement of Design Margin for Even-Stage Ring Oscillators with CMOS Latch
2011   

Research Grants & Projects

 
-

Patents

 
CMIS SEMICONDUCTOR NONVOLATILE STORAGE CIRCUIT
'US-7151706
SEMICONDUCTOR NONVOLATILE STORAGE CIRCUIT(US,EU,CN,KR,JP)
CMIS SEMICONDUCTOR NONVOLATILE STORAGE CIRCUIT
'US-7248507
METHOD FOR EVALUATING SRAM MEMORY CELL AND MEDIUM RECORDING EVALUATION PROGRAM OF SRAM MEMORY CELL COMPUTER READABLY
US8,169,813 B2
METHOD FOR EVALUATING SRAM MEMORY CELL AND MEDIUM RECORDING EVALUATION PROGRAM OF SRAM MEMORY CELL COMPUTER READABLY
10-1452013