Reflecting various physical phenomena of the primary visual cortex (V1) in hierarchical approaches has become prevalent over the years when the semiconductor miniaturization reaches its limit. In this paper, we propose a V1 hardware model to extract features. Our architecture with the edge, slit, left-right parallax, XY movement direction, and approach detection functions are a partial mimic from V1. The fundamental of the model is the sum of absolute differences and the AND function of the slit angles, which are increased gradually every 22.5° in the range of 0° to 157.5°. The handwritten letter recognition application is the first application that is assessed by replacing the first convolutional layer with the slit detection function. Our model is evaluated on Xilinx Zynq-7020 FPGA by the Vivado HLS tool. We reduce 46% in latency and 30% hardware resources at a 97.34% accuracy with other works on the MNIST database. It is therefore suggested that the proposal demonstrates high-efficiency energy in the hardware architecture.