Masahiro Iida

Profile Information

Affiliation: Professor, Research and Education Institute for Semiconductors and Informatics, Kumamoto University

Degree: Doctor of Engineering(Kumamoto University)

J-GLOBAL ID: 200901048049866454
researchmap Member ID: 5000050953

Research Interests

Research Areas

Research History

Apr, 2024 - Present

Professor, Division of Semiconductors, Kumamoto University, Research and Education Institute for Semiconductors and Informatics
Apr, 2018 - Mar, 2023

Professor, Division of Informatics and Energy, Kumamoto Univ. Faculty of Advanced Science and Technology
Apr, 2020 - Mar, 2022

Visiting Researcher, Center for Computational Science (R-CCS), RIKEN(The Institute of Physical and Chemical Research)
Jan, 2016 - Mar, 2018

Professor, Graduate School of Science and Technology(Engineering group),Kumamoto University
Apr, 2007 - Dec, 2015

Associate Professor, Graduate School of Science and Technology(Engineering group),Kumamoto University
Feb, 2003 - Mar, 2007

Associate Professor, Faculty of Engineering, Kumamoto University

Education

Apr, 1999 - Mar, 2002

Kumamoto University
Apr, 1995 - Mar, 1997

Kyushu Institute of Technology
Apr, 1984 - Mar, 1988

School of Engineering, Tokyo Denki University

Committee Memberships

Awards

Nov, 2018

General Graph Deepest Improvement Award, CANDAR Organizing Committee

Teruaki KITASUKA, Masahiro IIDA
Nov, 2017

General Graph Widest Improvement Award & Grid Graph Deepest Improvement Award, CANDAR Organizing Committee

Takayuki MATSUZAKI, Teruaki KITASUKA, Masahiro IIDA
Jun, 2017

Best Poster Award, High-level Synthesis based on Parallel Design Patterns using a Functional Language, International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2017)

Morihiro KUGA, Kansuke FUKUDA, Momtoki AMAGASAKI, Masahiro IIDA, Toshinori SUEYOSHI
Nov, 2016

Widest Improvement Awards in Graph Golf 2016, CANDAR Organizing Committee

Takayuki MATSUZAKI, Teruaki KITASUKA, Masahiro IIDA
Jun, 2015

論文賞, システムLSI搭載FPGA-IPコア向け物理故障検出および回避方法, 電子情報通信学会

尼崎太樹, 西谷祐樹, 井上万輝, 飯田全広, 久我守弘, 末吉敏則
Jun, 2015

優秀論文賞, Fault-tolerant FPGA: Architectures and design for Programmable Logic Intellectual Property Core in SoC, 電子情報通信学会リコンフィギャラブルシステム研究会

M. Amagasaki, Q. Zhao, M. Iida, M. Kuga, T. Sueyoshi
Sep, 2014

研究会優秀講演賞, Zyndroid: Android アプリケーションのHW/SW協調実行プラットフォーム, リコンフィギャラブルシステム研究専門委員会

眞下達, 久我守弘, 尼崎太樹, 飯田全広, 末吉敏則
Dec, 2012

アイデア優秀賞, ハイブリッド太陽光証明システム, ソーラーエネルギー等事業推進協議会

飯田全広
Nov, 2011

デザインガイアポスタ賞, 二重冗長ソフトコアプロセッサにおけるソフトエラーの高速復旧技, 電子情報通信学会および情報処理学会

一ノ宮佳裕, 藤野誠, 尼崎太樹, 久我守弘, 飯田全広, 末吉敏則
Nov, 2009

情報・システムソサイエティ活動功労賞, リコンフィギャラブルシステム研究会運営及び英文論文誌・和文論文誌編集への貢献

飯田全広
Apr, 2007

第9回LSI IPデザインアワード研究助成賞, 粒度可変構造を持つリコンフィギャラブルIP

尼崎太樹, 飯田全広, 末吉敏則
Jan, 2007

第14回FPGA/PLD Design Conference 優秀論文賞, 粒度可変構造を持つ再構成論理セル向けマッピング手法の評価

山口良一, 中山英明, 尼崎太樹, 松山和憲, 飯田全広, 末吉敏則
Jan, 2006

第13回FPGA/PLD Design Conference ユーザプレゼンテーション優秀論文賞, 粒度可変構造を持つ再構成論理セルアーキテクチャの提案

尼崎太樹, 中山英明, 濱邊直人, 飯田全広, 末吉敏則

Papers

Evaluation of the Second FPGA-IP Prototype for MEC Devices and its Improvements

MORIHIRO KUGA, MASAHIRO SUMITA, SEN GEN, MASAHIRO IIDA

Proc. of Asia Pacific Conference on Robot IoT System Development and Platform 2023 (APRIS2023), 67-68, Nov, 2023 Peer-reviewedLast author
Towards the Design of Locally Differential Private Hardware System for Edge Computing

Kaito Taguchi, Kouichi Sakurai, Masahiro Iida

Proc. of the Tenth International Symposium on Computing and Networking, Nov, 2022 Peer-reviewedLast author
Streaming Accelerator Design for Regular Expression on CPU+FPGA Embedded System

Hendarmawan, Morihiro Kuga, Masahiro Iida

ECTI Transactions on Computer and Information Technology (ECTI-CIT), 16(4) 448-459, Oct 11, 2022 Peer-reviewedLast author
An eFPGA Generation Suite with Customizable Architecture and IDE

KUGA Morihiro, ZHAO Qian, NAKAZATO Yuya, AMAGASAKI Motoki, IIDA Masahiro

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, advpub(3) 560-574, Oct, 2022 Peer-reviewedLast author
A Posit Based Multiply-accumulate Unit with Small Quire Size for Deep Neural Networks

Nakahara Yasuhiro, Masuda Yuta, Kiyama Masato, Amagasaki Motoki, Iida Masahiro

IPSJ Transactions on System LSI Design Methodology, 15 16-19, Aug, 2022 Peer-reviewedLast author
Reconfigurable Neural Network Accelerator and Simulator for Model Implementation

NAKAHARA Yasuhiro, KIYAMA Masato, AMAGASAKI Motoki, ZHAO Qian, IIDA Masahiro

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E105.A(3) 448-458, Mar 1, 2022 Peer-reviewedLast author
Automatic executable code generation for DNN accelerator ReNA.

Yuta Masuda, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida

Ninth International Symposium on Computing and Networking, 107-113, Nov, 2021 Peer-reviewedLast author
Automation of Domain-specific FPGA-IP Generation and Test

Yuya Nakazato, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga

Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Jun 21, 2021 Peer-reviewed
Translation Rules of Regular Expression Code for Hardware Accelerator

Proceedings of Asia Pacific Conference on Robot IoT System Development and Platform, (2020) 51-58, Mar 15, 2021 Peer-reviewedLast author
Development of Quantized DNN Library for Exact Hardware Emulation.

Masato Kiyama, Motoki Amagasaki, Masahiro Iida

arXiv, abs/2106.08892(400(VLD2020 67-91)), 2021 Last author
Relationship between Recognition Accuracy and Numerical Precision in Convolutional Neural Network Models.

Yasuhiro Nakahara, Masato Kiyama, Motoki Amagasaki, Masahiro Iida

IEICE Trans. Inf. Syst., 103-D(12) 2528-2529, Dec, 2020 Peer-reviewedLast author
Image Search System Based on Feature Vectors of Convolutional Neural Network

Mery Diana, Motoki Amagasaki, Masahiro Iida

2020 IEEE REGION 10 CONFERENCE (TENCON), Nov 16, 2020 Peer-reviewedLast author
Architecture-aware Cost Function for 3D FPGA Placement Using Convolutional Neural Network

Q. Zhao, M. Amagasaki, M. Iida, T. Yoshida

Proceedings of the Eighth International Symposium on Computing and Networking, 235-241, Nov, 2020 Peer-reviewed
A Microcode-based Control Unit for Deep Learning Processors.

Qian Zhao 0001, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida, Takaichi Yoshida

2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 139-142, May, 2020 Peer-reviewed
R-GCN Based Function Inference for Gate-level Netlist.

Motoki Amagasaki, Hiroki Oyama, Yuichiro Fujishiro, Masahiro Iida, Hiroaki Yasuda, Hiroto Ito

IPSJ Trans. Syst. LSI Des. Methodol., 13 69-71, Feb, 2020 Peer-reviewed
Low-Cost Image Search System on Off-Line Situation

Mery Diana, Juntaro Chikama, Motoki Amagasaki, Masahiro Iida

Electronics, 9(1) 153-153, Jan 14, 2020 Peer-reviewedLast author
Routing Resources Reduction of Virtual FPGA for Specific Application Sets

Myint Theingi, Takanori Ito, Amagasaki Motoki, Zhao Qian, Iida Masahiro

International Journal of Innovative Computing, Information and Control, 16(01) 395, 2020
A SLM-based overlay architecture for fine-grained virtual FPGA

Theingi Myint, Motoki Amagasaki, Qian Zhao, Masahiro Iida

IEICE Electronics Express, 16(24) 20190610-20190610, Dec, 2019 Peer-reviewedLast author
EVALUATION OF ROUTING AREA REDUCTION FOR FINE-GRAINED OVERLAY VIRTUAL FPGA

Theingi Myint, Ito Takanori, Motoki Amagasaki, Qian Zhao, Masahiro Iida

International Journal of Innovative Computing, Information and Control (IJICIC), Dec, 2019 Peer-reviewedLast author
A Novel SLM-based Virtual FPGA Overlay Architecture

Theingi Myint, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Masato Kiyama

Proc. of IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip(IEEE MCSoC-2019), 74-80, Oct, 2019 Peer-reviewed

Misc.

273

Adopting Open-source Logic Synthesizer for the original FPGA-IP

Sen Gen, Masahiro SUMITA, Morihiro KUGA, Masahiro IIDA

Proc. 2023 Joint Conference of Electrical, Electronics and Information Engineers in Kyusyu (JCEEE-Kyushu 2023), Sep, 2023 Last author
Evaluation of the static timing analysis of an FPGA-IP prototype chip for MEC devices

Masahiro SUMITA, Morihiro KUGA, Masahiro IIDA

Proc. 2023 Joint Conference of Electrical, Electronics and Information Engineers in Kyusyu (JCEEE-Kyushu 2023), Sep, 2023 Last author
LSI化の検討に使用するSNNシミュレータSULIの開発と評価

小崎裕二郎, 坂本圭, 飯田全広

電子情報通信学会技術研究報告(Web), 122(373(NLP2022 81-106)), 2023
A Chip Testing Methodology for RISC-V SoC Using Jupyter Notebook

小島拓也, 小島拓也, 亀井愛佳, 矢内洋祐, 天野英晴, 久我守弘, 飯田全広

情報処理学会研究報告(Web), 2023(ARC-252), 2023
RISC-V MPおよびSLM再構成ロジックを混載した「SLMLET」チップの電力評価

矢内洋祐, 小島拓也, 小島拓也, 奥原颯, 天野英晴, 久我守弘, 飯田全広

電子情報通信学会技術研究報告(Web), 123(145(CPSY2023 8-26)), 2023
FPGAとRISC-Vプロセッサを搭載したSoC向けHW/SW設計フローと実機評価

小島拓也, 矢内洋祐, 奥原颯, 天野英晴, 久我守弘, 飯田全広

電子情報通信学会技術研究報告(Web), 123(191(RECONF2023 19-32)), 2023
Tag-Less Compression for FPGA Configuration Data

Souhei Takagi, Naoya Niwa, Yusuke Yanai, Hideharu Amano, Motoki Amagasaki, Yuya Nakazato, Masahiro Iida

Poster, SASIMI2022, Oct, 2022 Peer-reviewedLast author
計算資源制約下における差分プライバシー強化手法の提案と有効性の検証

田口魁人, 櫻井幸一, 飯田全広

Oct, 2022 Last author
Proposal and evaluation of Combined Posit MAC unit (CPMAC) for both DNN inference and training

増田雄太, 中原康宏, 木山真人, 飯田全広

電子情報通信学会技術研究報告(Web), 122(174) 29-34, Sep, 2022 Last author
FPGA implementation of small area sum-of-products arithmetic unit for Posit and consideration of its introduction into AI chip ReNA

中原康宏, 増田雄太, 木山真人, 飯田全広

電子情報通信学会技術研究報告(Web), 122(174) 23-28, Sep, 2022 Last author
FPL Demo: An FPGA-IP Prototype Chip for MEC devices

Morihiro Kuga, Masahiro Iida, Hideharu Amano

International Conference on Field Programmable Logic and Applications(FPL2022), Sep, 2022 Peer-reviewed
Proposal and Evaluation of a Method for Enhancing Local Differential Privacy in IoT Devices

田口魁人, 櫻井幸一, 飯田全広

情報処理学会研究報告(Web), 2022(CSEC-98), Jul, 2022
Preliminary Evaluation of “SLMLET” Chip with Mixed RISC-V MP and SLM Reconfiguration Logic

矢内洋祐, 小島拓也, 奥原颯, 天野英晴, 飯田全広

電子情報通信学会技術研究報告(Web), 122(133(CPSY2022 1-16)), Jul, 2022
A study of an accelerator for CNN inference on FPGA clusters

境琳太郎, 境琳太郎, 中原康宏, 中原康宏, 佐野健太郎, 飯田全広, 飯田全広

電子情報通信学会技術研究報告(Web), 122(60) 48-49, Jun, 2022 Last author
The Verification of an FPGA-IP prototype chip for MEC Devices

久我守弘, 中里優弥, ZHAO Qian, 尼崎太樹, 飯田全広

電子情報通信学会大会講演論文集(CD-ROM), 2022, Mar, 2022 Last author
Configuration Data Compression for SLM Fine-grained Reconfigurable Logic

高木颯平, 小島拓也, 天野英晴, 久我守弘, 飯田全広

電子情報通信学会技術研究報告(Web), 123(258(VLD2023 30-79)), Mar, 2022 Last author
Configuration Data Compression for SLM Fine-grained Reconfigurable Logic

高木颯平, 丹羽直也, 四釜快弥, 矢内洋祐, 天野英晴, 中里優弥, 尼崎太樹, 飯田全広

電子情報通信学会技術研究報告(Web), 121(425(CPSY2021 45-65)), 2022
A Study on Technology Mapping Method for Scalable Logic Module

木内泉美, 中里優弥, ZHAO Qian, 飯田全広

電子情報通信学会技術研究報告(Web), 121(344) 108-113, Jan, 2022 Last author
A study of an accelerator for CNN inference on FPGA clusters

境琳太郎, 境琳太郎, 中原康宏, 中原康宏, 佐野健太郎, 飯田全広, 飯田全広

電子情報通信学会技術研究報告(Web), 121(344) 61-6, Jan, 2022 Last author
Basic evaluation of ReNA, a DNN accelerator using numerical representation posit

中原康宏, 増田雄太, 木山真人, 尼崎太樹, 飯田全広

電子情報通信学会技術研究報告(Web), 121(277(VLD2021 17-48)), Dec, 2021 Last author

Books and Other Publications

FPGA原理和結構（中国語版）

天野英晴 (Role: Joint author, 2章，5章)

人民郵電出版社, Mar, 2019
Principles and Structures of FPGAs

Eds. Hideharu AMANO (Role: Joint author, Chap2, Chap5)

Springer, Sep, 2018
はじめての論理回路

飯田全広

（株）近代科学社, Jul, 2018
FPGAの原理と構成

天野英晴 (Role: Joint author, 第2章，第5章)

（株）オーム社, Apr, 2016
リコンフィギャラブルシステム

末吉敏則, 天野英晴 (Role: Joint author, 第4章)

（株）オーム社, 2005

Presentations

ストリーミングによるデータベースフィルタ処理の一検討

中川裕貴, 久我守弘, 尼崎太樹, 飯田全広, 末吉敏則

信学技報 RECONF2018-33, vol.118, no.215, pp79-84, Sep. 2018., Sep 18, 2018
A Case Study on Complex Event Processing over low cost ARM+FPGA Boards

Hendarmawan, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

信学技報 RECONF2018-21, vol.118, no.215, pp13-18, Sep. 2018., Sep 17, 2018
グラフ畳み込みネットワークを用いたネットリスト機能推定の検討

小山大輝, 尼崎太樹, 飯田全広, 安田紘晃, 伊藤寛人

信学技報 VLD2018-44, vol.118, no.334, pp31-36, Dec. 2018.

Teaching Experience

Professional Memberships

Works

Research Projects

A Study of Recurrent Reconfigurable Neuromorphic Accelerator

Project for Innovative AI Chips and Next-Generation Computing Technology Development Development of Innovative AI Edge Computing Technologies, New Energy and Industrial Technology Development Organization, Oct, 2018 - Sep, 2019

IIDA Masahiro
Research and Development of High-speed Logic Emulator for Ultra-Scale Integrated Circuit

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (C), Japan Society for the Promotion of Science, Apr, 2016 - Mar, 2019

Kuga Morihiro, ZHAO Qian, AMAGASAKI Motoki, IIDA Masahiro, SUEYOSHI Toshinori
大規模並列計算システム向け低遅延ネットワーク・トポロジに関する研究

科学研究費補助金・基盤研究(C), 2017 - 2019

飯田全広
リコンフィギャラブルシステム向けプログラミングモデルに関する研究

科学研究費補助金・挑戦的萌芽研究, 2011 - 2013

飯田全広
ディペンダビリティを備えた高性能FPGAアーキテクチャに関する研究

科学研究費補助金・基盤研究(B), 2011 - 2013

飯田全広
再構成可能デバイス向け統合EDAツールに関する研究

科学研究費補助金・基盤研究(B), 2006 - 2008

飯田全広
再構成可能な論理デバイスを用いた低消費エネルギ化手法に関する研究

科学研究費補助金・基盤研究(C), 2004 - 2005

飯田全広
自律再構成可能な論理デバイスの実現

ＪＳＴ戦略的創造研究推進制度（個人研究型）（個人研究推進事業：さきがけ研究２１‐ＰＲＥＳＴＯ）, 2002 - 2005

飯田全広
Autonomous and Dynamically Reconfigurable Logic Device

JST Basic Research Programs (Precursory Research for Embryonic Science and Technology :PRESTO), 2002 - 2005

Industrial Property Rights

特許5937550 プログラマブル論理回路およびその構成方法

末吉敏則, 飯田全広, 久我守弘, 尼崎太樹, 柳田恭成
特許5701054 リコンフィギャラブルロジック, 並びに, これを用いたプログラマブル論理回路装置, 及び, テクノロジマッピング手法

末吉敏則, 飯田全広, 尼崎太樹, 加藤宏太, 市田善信
特許5558269 プログラマブル論理回路のエラー訂正回路

末吉敏則, 飯田全広, 尼崎太樹, 一ノ宮佳裕
特許5523988 プログラマブル論理回路装置およびその回路決定方法

末吉敏則, 飯田全広, 尼崎太樹, 岡本康裕
特許United States Patent 8,587,336B2 RECONFIGURABLE LOGIC BLOCK, PROGRAMMABLE LOGIC DEVICE PROVIDED WITH THE RECONFIGURABLE LOGIC BLOCK, AND METHOD OF FABRICATING THE RECONFIGURABLE LOGIC BLOCK

Toshinori SUEYOSHI, Masahiro IIDA, Motoki AMAGASAKI, Kazuhiko TAKEDA, Taketo HEISHI, Nobuharu SUZUKI
特許4914423 相互接続構造および論理回路装置

末吉敏則, 飯田全広, 尼崎太樹, 井上万輝, 平松達夫
特許4621424 プログラマブル論理回路およびプログラマブル論理回路の配線構造

飯田全広
特許4438000 リコンフィギャラブルロジックブロック，リコンフィギャラブルロジックブロックを備えるプログラマブル論理回路装置，およおよび，リコンフィギャラブルロジックブロックの構成方法

末吉敏則, 飯田全広, 尼崎太樹, 武田和彦, 瓶子岳人, 鈴木伸治
特許United States Patent 6,812,737 PROGRAMMABLE LOGIC CIRCUIT DEVICE HAVING LOOK UP TABLE ENABLING TO REDUCE IMPLEMENTATION AREA

Toshinori SUEYOSHI, Masahiro IIDA
特許3580785 ルックアップテーブル，ルックアップテーブルを備えるプログラマブル論理回路装置，およびルックアップテーブルの構成方法

末吉敏則, 飯田全広

Profile Information

Research Interests

Research Areas

Research History

Education

Committee Memberships

Awards

Papers

Misc.

Books and Other Publications

Presentations

Teaching Experience

Professional Memberships

Works

Research Projects

Industrial Property Rights

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