MISC

2006年2月

Fabrication and characterization of vertical-type double-gate metal-oxide-semiconductor field-effect transistor with ultrathin Si channel and self-aligned source and drain

APPLIED PHYSICS LETTERS
  • M Masahara
  • ,
  • YX Liu
  • ,
  • K Endo
  • ,
  • T Matsukawa
  • ,
  • K Sakamoto
  • ,
  • K Ishii
  • ,
  • S O'uchi
  • ,
  • E Sugimata
  • ,
  • H Yamauchi
  • ,
  • E Suzuki

88
7
開始ページ
0721031-0721033
終了ページ
記述言語
英語
掲載種別
DOI
10.1063/1.2173715
出版者・発行元
AMER INST PHYSICS

A fabrication technique for a vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) with a standing-up ultrathin channel (UTC) and self-aligned source and drain (S/D) is proposed. A 20 nm thick vertical UTC with low channel thickness fluctuation was formed on a (110)-oriented Si substrate using orientation-dependent wet etching. The top and bottom S/D were self-aligned to the DGs by using a combination of ion implantation and solid-phase diffusion. The fabricated vertical DG MOSFETs revealed that the channel thickness less influences the threshold voltage. Furthermore, a low sub-threshold slope of 68.8 mV/decade was achieved with a channel thickness of 20 nm.

Web of Science ® 被引用回数 : 8

リンク情報
DOI
https://doi.org/10.1063/1.2173715
Web of Science
https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:000235393700049&DestApp=WOS_CPL
ID情報
  • DOI : 10.1063/1.2173715
  • ISSN : 0003-6951
  • Web of Science ID : WOS:000235393700049

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