MISC

2006年

縦型ダブルゲートMOSFETデバイス技術

電気学会誌
  • 昌原 明植
  • ,
  • 柳 永〓
  • ,
  • 遠藤 和彦
  • ,
  • 松川 貴
  • ,
  • 鈴木 英一

126
6
開始ページ
702
終了ページ
707
記述言語
日本語
掲載種別
DOI
10.1541/ieejeiss.126.702
出版者・発行元
The Institute of Electrical Engineers of Japan

The Silicon device technology is facing to several difficulties. Especially, explosion of power consumption due to short channel effects (SCEs) becomes the biggest issue in further device scaling down. Fortunately, double-gate (DG) MOSFETs have promising potential to overcome this obstacle. The DG-MOSFET is recognized to be the most scalable MOSFET for its high SCEs immunity. In addition, independent DG-MOSFET (4T-DG-MOSFET) has great advantage to enable the threshold voltage control for the flexible power management. Through this work, we have realized ideal DG-MOSFETs using newly-developed vertical DG-MOSFET device technology. This article presents the effectiveness of the vertical DG-MOSFETs in future high-performance and ultra-low-power CMOS circuits.

リンク情報
DOI
https://doi.org/10.1541/ieejeiss.126.702
CiNii Articles
http://ci.nii.ac.jp/naid/10017582622
CiNii Books
http://ci.nii.ac.jp/ncid/AN10065950
URL
http://id.ndl.go.jp/bib/7979234
URL
https://jlc.jst.go.jp/DN/JALC/00279446721?from=CiNii
ID情報
  • DOI : 10.1541/ieejeiss.126.702
  • ISSN : 0385-4221
  • CiNii Articles ID : 10017582622
  • CiNii Books ID : AN10065950

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