MISC

2006年3月

Fabrication of a vertical-channel double-gate metal-oxide-semiconductor field-effect transistor using a neutral beam etching

JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS
  • K Endo
  • ,
  • S Noda
  • ,
  • M Masahara
  • ,
  • T Kubota
  • ,
  • T Ozaki
  • ,
  • SJ Samukawa
  • ,
  • YX Liu
  • ,
  • K Ishii
  • ,
  • Y Ishikawa
  • ,
  • E Sugimata
  • ,
  • T Matsukawa
  • ,
  • H Takashinia
  • ,
  • H Yamauchi
  • ,
  • E Suzuki

45
8-11
開始ページ
L279
終了ページ
L281
記述言語
英語
掲載種別
DOI
10.1143/JJAP.45.L279
出版者・発行元
INST PURE APPLIED PHYSICS

A vertical ultrathin-channel (UTC) formation process using a low-energy neutral beam etching (NBE) for a double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is proposed for the first time. The NBE can perfectly eliminate the charge build-up and photon radiation damages from the plasma. By utilizing the NBE, fin-type vertical MOSFETs with damage-less smooth sidewalls were successfully fabricated. The fabricated FinFFTs realized higher electron mobility than that using a conventional reactive ion etching. The improved mobility is well explained by the atomically-flat surface utilizing by the NBE.

Web of Science ® 被引用回数 : 9

リンク情報
DOI
https://doi.org/10.1143/JJAP.45.L279
Web of Science
https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:000236562200022&DestApp=WOS_CPL
ID情報
  • DOI : 10.1143/JJAP.45.L279
  • ISSN : 0021-4922
  • Web of Science ID : WOS:000236562200022

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