論文

査読有り 招待有り
2021年5月7日

(Invited) Layer Transfer Technology for Stacked Multi-Channel Semiconductor-on-Insulator Platform

ECS Transactions
  • Wen Hsin Chang
  • ,
  • T.-Z. Hong
  • ,
  • P.-J. Sung
  • ,
  • Toshifumi Irisawa
  • ,
  • Hiroyuki Ishii
  • ,
  • Y.-J. Lee
  • ,
  • Tatsuro Maeda

102
4
開始ページ
17
終了ページ
26
記述言語
掲載種別
研究論文(学術雑誌)
DOI
10.1149/10204.0017ecst
出版者・発行元
The Electrochemical Society

Continuous scaling of device dimension pushed CMOS technology based on Si materials to its physical limit, alternative high mobility channels such as (Si)Ge and III-V materials have been considered to replace Si to further enhance CMOS performance. In the meantime, ultrathin body (UTB) semiconductor-on-insulator is attractive for fabricating nanowire/nanosheet channel structures for improved gate controllability and immunity against short channel effects in the ultra-scaled high performance and low power dissipation CMOS. To realize multiple channels stacked semiconductor-on-insulator platform on current mainstream Si wafers, layer transfer technology utilizing direct bonding and selective etching was developed to integrate UTB (Si)Ge or InGaAs channels on Si. The devices fabricated with multiple stacked nanowire/nanosheet channels have also been demonstrated through sequential or monolithic 3D integration approach, showing great potential of layer transfer technology for ultimate CMOS structures.

リンク情報
DOI
https://doi.org/10.1149/10204.0017ecst
URL
https://iopscience.iop.org/article/10.1149/10204.0017ecst
URL
https://iopscience.iop.org/article/10.1149/10204.0017ecst/pdf
ID情報
  • DOI : 10.1149/10204.0017ecst
  • ISSN : 1938-5862
  • eISSN : 1938-6737
  • ORCIDのPut Code : 94167943

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