菅野卓雄 (Takuo Sugano) - マイポータル

基本情報

所属: 東京大学 (名誉教授)

学位: 工学博士、工学修士

J-GLOBAL ID: 200901027204363424
researchmap会員ID: 5000092035

研究キーワード

半導体電子工学

研究分野

ものづくり技術（機械・電気電子・化学工学） / 電子デバイス、電子機器 /

学歴

- 1959年

東京大学大学院, 工学系研究科, 電気工学専門課程博士課程

論文

Improvement of electrical characteristics of local BOX MOSFETs by heavily doped structures and elucidation of the related mechanism

Tatsuya Yamada, Yoshikata Nakajima, Tatsuro Hanajiri, Toru Toyabe, Takuo Sugano

JOURNAL OF COMPUTATIONAL ELECTRONICS 13(2) 400-407 2014年6月査読有り
Suppression of Drain-Induced Barrier Lowering in Silicon-on-Insulator MOSFETs Through Source/Drain Engineering for Low-Operating-Power System-on-Chip Applications (vol 60, pg 260, 2013)

Tatsuya Yamada, Yoshikata Nakajima, Tatsuro Hanajiri, Takuo Sugano

IEEE TRANSACTIONS ON ELECTRON DEVICES 60(12) 4281-4283 2013年12月査読有り
Quantitative Extraction of Electric Flux in the Buried-Oxide Layer and Investigation of Its Effects on MOSFET Characteristics

Tatsuya Yamada, Shumpei Abe, Yoshikata Nakajima, Tatsuro Hanajiri, Toru Toyabe, Takuo Sugano

IEEE TRANSACTIONS ON ELECTRON DEVICES 60(12) 3996-4001 2013年12月査読有り
Suppression of Drain-Induced Barrier Lowering in Silicon-on-Insulator MOSFETs Through Source/Drain Engineering for Low-Operating-Power System-on-Chip Applications

Tatsuya Yamada, Yoshikata Nakajima, Tatsuro Hanajiri, Takuo Sugano

IEEE TRANSACTIONS ON ELECTRON DEVICES 60(1) 260-267 2013年1月査読有り
Local-Stress-Induced Trap States in SOI Layers With Different Levels of Roughness at SOI/BOX Interfaces

Yoshikata Nakajima, Yukitoshi Watanabe, Tatsuro Hanajiri, Toru Toyabe, Takuo Sugano

IEEE ELECTRON DEVICE LETTERS 32(3) 237-239 2011年3月査読有り
In-depth profiling of electron trap states in silicon-on-insulator layers and local mechanical stress near the silicon-on-insulator/buried oxide interface in separation-by-implanted-oxygen wafers

Yoshikata Nakajima, Takahiro Toda, Tatsuro Hanajiri, Toru Toyabe, Takuo Sugano

JOURNAL OF APPLIED PHYSICS 108(12) 124505 2010年12月査読有り
Discussion of origins of high-density trap states in SIMOX wafers

Yoshikata Nakajima, Takahiro Toda, Tatsuro Hanajiri, Toru Toyabe, Takuo Sugano

ULIS 2009: 10TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION OF SILICON 185-188 2009年査読有り
Suppression of DIBL in deca-nano SOI MOSFETs by controlling permittivity and thickness of BOX layers

Shunpei Abe, Yoshiyasu Miyazawa, Yoshikata Nakajima, Tatsuro Hanajiri, Toru Toyabe, Takuo Sugano

ULIS 2009: 10TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION OF SILICON 329-332 2009年査読有り
Drive current enhancement in silicon-on-quartz MOSFETs

Yoshikata Nakajima, Kenji Sasaki, Tatsuro Hanajiri, Toru Toyabe, Takuo Sugano

IEEE ELECTRON DEVICE LETTERS 29(8) 944-945 2008年8月査読有り
Characterization of distribution of trap states in silicon-on-insulator layers by front-gate characteristics in n-channel SOI MOSFETs

Kenji Kajiwara, Yoshikata Nakajima, Tatsuro Hanajiri, Toru Toyabe, Takuo Sugano

IEEE TRANSACTIONS ON ELECTRON DEVICES 55(7) 1702-1707 2008年7月査読有り
Erratum: A new measurement technique for the characterization of carrier lifetime in thin SOI MOSFETs (Thin Solid Films (2004) 462 (6-10))

Yoshikata Nakajima, Hideki Tomita, Kenichi Aoto, Kenji Sasaki, Tatsuro Hanajiri, Toru Toyabe, Takitaro Morikawa, Takuo Sugano

Thin Solid Films 488(1-2) 337-339 2005年9月22日査読有り
A new measurement technique for the characterization of carrier lifetime in thin SOI MOSFETs

Yoshikata Nakajima, Hideki Tomita, Kenichi Aoto, Kenji Sasaki, Tatsuro Hanajiri, Toru Toyabe, Takitaro Morikawa, Takuo Sugano

Thin Solid Films 462-463 6-10 2004年9月
Characterization of trap states at silicon-on-insulator (SOI)/buried oxide (BOX) interface by back gate transconductance characteristics in SOI MOSFETs

Yoshikata Nakajima, Hideki Tomita, Kenichi Aoto, Nobuhiro Ito, Tatsuro Hanajiri, Toru Toyabe, Takitaro Morikawa, Takuo Sugano

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers 42(4 B) 2004-2008 2003年

MISC

Correlation between high-density trap states and local stress near SOI/BOX interface in SIMOX wafers

Yoshikata Nakajima, Yukitoshi Watanabe, Tatsuro Hanajiri, Toru Toyabe, Takuo Sugano

2009 International Semiconductor Device Research Symposium, ISDRS '09 2009年査読有り
工学における量子力学 (量子力学と先端技術<特集>)

菅野卓雄

数理科学 25(4) p5-11 1987年4月

共同研究・競争的資金等の研究課題

ナノエレクトロニクス

ＪＳＴ戦略的創造研究推進制度（研究チーム型）（戦略的基礎研究推進事業：ＣＲＥＳＴ） 1998年 - 2006年
微小傾角基板を用いた単一電子トンネル・デバイスの研究

日本学術振興会科学研究費助成事業一般研究(B) 1993年 - 1995年

菅野卓雄, 神田洋三, 村山洋一