© 1980-2012 IEEE. Through-silicon-vias (TSVs) with a diameter of 3μm and high aspect ratio of 15 are successfully fabricated based on a low-cost and low-temperature process involving spin coating of polyimide liner, electroless plating of Ni barrier/seed layer, and electroplating of Cu, which is suitable for via-middle/via-last processes that have a more stringent thermal budget. A novel eccentric spin coating technique is proposed for liner formation, which greatly improves the wafer-level uniformity and reduces the bottom dielectric thickness of the vias located close to the center of the wafer. The measured results show that the fabricated TSVs exhibit low depletion capacitance of 33 fF, low leakage current of 2.2 pA at 20 V, and good barrier property against Cu diffusion even after annealing at 400°C, indicating the feasibility of the proposed technique in high density and low area penalty 3-D large-scale integrated circuits.