NATSUI Masanori

J-GLOBAL         Last updated: Dec 20, 2019 at 20:17
 
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Name
NATSUI Masanori
URL
http://db.tohoku.ac.jp/whois/e_detail/8f0d1dcaad8e3dd9434d73fd1f0b684e.html
Affiliation
Tohoku University
Section
Research Institute of Electrical Communication Laboratory for Brainware Systems New Paradigm VLSI System
Job title
Associate Professor
Degree
博士(情報科学)(Tohoku University)
Other affiliation
Tohoku University

Research Areas

 
 

Committee Memberships

 
Apr 2016
 - 
Today
多値論理研究会  庶務幹事
 
Apr 2016
 - 
Today
情報処理学会東北支部  広報幹事
 
Apr 2016
 - 
Today
電子情報通信学会集積回路研究専門委員会  幹事補佐
 

Awards & Honors

 
May 2012
Kenneth C. Smith Early Career Award for Microelectronics Research, MVL-TC, IEEE
 
May 2010
電子情報通信学会エレクトロニクスソサイエティ論文賞, 子情報通信学会エレクトロニクスソサイエティ
Winner: 鈴木大輔,夏井雅典,羽生貴弘
 
Aug 2003
IEEE Sendai Section Student Award, IEEE Sendai Section
 
Aug 2001
情報処理学会東北支部奨励賞, 情報処理学会東北支部
 

Published Papers

 
MTJ-Based Nonvolatile Logic-in-Memory Circuit with Feedback-Type Equal-Resistance Sensing Mechanism for Ternary Neural Network Hardware
M. Natsui and T. Hanyu
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference      Oct 2019   [Refereed]
Nonvolatile Logic LSI Design Technology and Its Application to AI Hardware
NATSUI Masanori
2019 International Conference on Solid State Devices and Materials (SSDM2019),Short Courses      Sep 2019   [Invited]
A 47.14μW 200MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications
M. Natsui, D. Suzuki, A. Tamakoshi, T. Watanabe, H. Honjo, H. Koike, T. Nasuno, Y. Ma, T. Tanigawa, Y. Noguchi, M. Yasuhira, H. Sato, S. Ikeda, H. Ohno, T. Endoh, and T. Hanyu
IEEE Journal of Solid State Circuits (JSSC)   54(11) 2991-3004   Aug 2019   [Refereed]
Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks
T. Chiba, M. Natsui, and T. Hanyu
Proceedings of the 49th International Symposium on Multiple-Valued Logic (ISMVL)   91-96   May 2019   [Refereed]
Design of an Energy-Efficient XNOR Gate Based on MTJ-Based Nonvolatile Logic-in-Memory Architecture for Binary Neural Network Hardware
M. Natsui, T. Chiba, and T. Hanyu
Japanese Journal of Applied Physics (JJAP)   58(SB) SBBB01-1-SBBB01-7   Apr 2019   [Refereed]
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJHybrid Technology Achieving 47.14μW Operation at 200MHz
M. Natsui, D. Suzuki, A. Tamakoshi, T. Watanabe, H. Honjo, H. Koike, T. Nasuno, Y. Ma, T. Tanigawa, Y. Noguchi, M. Yasuhira, H. Sato, S. Ikeda, H. Ohno, T. Endoh, and T. Hanyu
2019 IEEE International Solid-State Circuits Conference (ISSCC2019)   202-203   Feb 2019   [Refereed]
Design of MTJ-Based Nonvolatile Logic Gates for Quantized Neural Networks
M Natsui, T Chiba, and T Hanyu
Microelectronics Journal   82 13-21   Dec 2018   [Refereed]
MTJ-Based Nonvolatile Ternary Logic Gate for Quantized Convolutional Neural Networks
M. Natsui, T. Chiba and T. Hanyu
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference   2 pages   Oct 2018   [Refereed]
MTJ-Based Nonvolatile Logic Gate for Binarized Convolutional Neural Networks and Its Impact
M. Natsui, T. Chiba and T. Hanyu
Extended Abstracts of 2018 International Conference on Solid State Devices and Materials (SSDM2018)   109-110   Sep 2018   [Refereed]
Systematic Intrusion Detection Technique for In-Vehicle Network Based on Time-Series Feature Extraction
H. Suda, M. Natsui, and T. Hanyu
48th IEEE International Symposium on Multiple-Valued Logic (ISMVL2018)   56-61   May 2018   [Refereed]
M. Natsui, T. Endoh, H. Ohno, and T. Hanyu
China Semiconductor Technology International Conference (CSTIC)   54   Mar 2018   [Invited]
Data-Stream-Aware Computing for Highly Dependable VLSI Systems
M. Natsui, H. Suda and T. Hanyu
The 5th International Symposium on Brainware LSI   8   Feb 2018
Design of a memory-access controller with 3.71-times-enhanced energy efficiency for Internet-of-Things-oriented nonvolatile microcontroller unit
M. Natsui and T. Hanyu
Japanese Journal of Applied Physics   57(4S) 04FN03-1-04FN03-5   2018   [Refereed]
Energy-Efficient Data-Access Technique for an Ultra Low-Power Nonvolatile Microcontroller Unit
M. Natsui and T. Hanyu
3rd ImPACT International Symposium on Spintronic Memory, Circuit and Storage   57   Sep 2017
Energy-Efficient High-Performance Nonvolatile VLSI Processor with a Temporary-Data Reuse Technique
M. Natsui and T. Hanyu
2017 International Conference on Solid State Devices and Materials (SSDM2017)   977-978   Sep 2017   [Refereed]
Design of a Variation-Resilient Single-Ended Nonvolatile 6-Input Lookup Table Circuit with a Redundant-MTJ-Based Active Load for Smart IoT Applications
D. Suzuki, M. Natsui, A. Mochizuki, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu
IET Electronics Letters   53(7) 456-458   Mar 2017   [Refereed]
Fabrication of an MTJ-Based Nonvolatile Logic-in-Memory LSI with Content-Aware Write Error Masking Scheme Achieving 92% Storage Capacity and 79% Power Reduction
M. Natsui, A. Tamakoshi, T. Endoh, H. Ohno, and T. Hanyu
Japanese Journal of Applied Physics   04CN01-1-04CN01-5   Mar 2017   [Refereed]
Fabrication of an MTJ-Based Nonvolatile Logic-in-Memory LSI with Content-Aware Write Error Masking Scheme Achieving 92% Storage Capacity and 79% Power Reduction
Masanori Natsui, Akira Tamakoshi, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
Japanese Journal of Applied Physics   56(4S) 04CN01-1-04CN01-5   Feb 2017   [Refereed]
Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, and Hideo Ohno
Proc. IEEE   104(10) 1844-1863   Oct 2016   [Refereed]
Highly Reliable MTJ-Based Motion-Vector Prediction Unit with Dynamic Write Error Masking Scheme
Masanori Natsui, Akira Tamakoshi, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
Proc. of 2016 International Conference on Solid State Devices and Materials   77-78   Sep 2016   [Refereed]
Masanori Natsui, Naoto Sugaya, and Takahiro Hanyu
14th IEEE International NEWCAS Conference (NEWCAS2016)   4112-1-4112-4   Jun 2016   [Refereed]
N. Sugaya, M.Natsui, and T.Hanyu
46th IEEE International Symposium on Multiple-Valued Logic (ISMVL2016)   72-77   May 2016   [Refereed]
M. Natsui, A. Tamakoshi, A. Mochizuki, H. Koike, H. Ohno, T. Endoh, and T. Hanyu
2016 IEEE International Symposium on Circuits and Systems(ISCAS2016)   1878-1881   May 2016   [Refereed]
Brain-Inspired Computing for Variation-Resilient VLSI System
M. Natsui, N. Sugaya, and T.Hanyu
The 3rd International Symposium on Brainware LSI   2   Feb 2016
T. Hanyu, M. Natsui, D. Suzuki, A. Mochizuki, N. Onizawa, S. Ikeda, T. Endoh, and H. Ohno
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference   57-59   Oct 2015   [Invited]
Fabrication of a 3000-6-Input-LUTs Embedded and Block-Level Power-Gated Nonvolatile FPGA Chip Using p-MTJ-Based Logic-in-Memory Structure
D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, H. Sato, S. Fukami, S. Ikeda, T. Endoh, H. Ohno and T. Hanyu
2015 Diguest of Technical Papers, Symp. VLSI Circuit   172-173   Jun 2015   [Refereed]
T. Akutsu, M. Natsui, and T. Hanyu
IEEE International Symposium on Multiple-Valued Logic (ISMVL 2015)   152-157   May 2015   [Refereed]
Spintronics-Based Nonvolatile Logic-in-Memory Architecture Towards an Ultra-Low-Power and Highly Reliable VLSI Computing Paradigm
Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, and Akira Mochizuki
Design, Automation & Test in Europe (DATE) 2015   8.5.3   Mar 2015   [Refereed][Invited]
Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
IEEE Journal of Solid-State Circuits (JSSC)   50(2) 476-489   Feb 2015   [Refereed]
Takahiro Hanyu, Daisuke Suzuki, Akira Mochizuki, Masanori Natsui, Naoya Onizawa, Tadahiko Sugibayashi, Shoji Ikeda, Tetsuo Endoh and Hideo Ohno
2014 IEEE International Electron Devices Meeting (IEDM2014)   28.2.1-28.2.3   Dec 2014   [Refereed][Invited]
Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Takahiro Hanyu
IEEE Trans. Magn.   50(11) 3402104~1-3402104~4   Nov 2014   [Refereed]
Daisuke Suzuki, Noboru Sakimura, Masanori Natsui, Akira Mochizuki, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
IEICE Electronics Express (ELEX)   11(13) 20140296-1-20140296-11   Jun 2014   [Refereed]
Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Hideo Sato, Shunsuke Fukami, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
Journal of Applied Physics   115(17) 17B742-1-17B742-3   Mar 2014   [Refereed]
Optimally Self-Terminated Compact Switching Circuit Using Continuous Voltage Monitoring Achieving High Read Margin for STT MRAM and Logic
Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, and Takahiro Hanyu
IEEE Intermag 2014   2506-2507   Mar 2014   [Refereed]
Masanori Natsui and Takahiro Hanyu
IEEE 44th International Symposium on Multiple-Valued Logic   243-247   Mar 2014   [Refereed]
Masanori Natsui and Takahiro Hanyu
12th IEEE International NEWCAS Conference (NEWCAS2014)   468-471   Mar 2014   [Refereed]
Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, and Takahiro Hanyu
Japanese Journal of Applied Physics (JJAP)   53(45) 04EM03-1-04EM03-5   Feb 2014   [Refereed]
N. Sakimura, R. Nebashi, M. Natsui, H. Ohno, T. Sugibayashi, and T. Hanyu
Journal of Applied Physics   115(17) 17B748-1-17B748-2   2014   [Refereed]
Fabrication of a Perpendicular-MTJ-Based Compact Nonvolatile Programmable Switch Using Shared-Write-Control-Transistor Structure
D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, K. Kinoshita, H. Sato, S. Fukami, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu
Abst. 58th Annual Conference on Magnetism and Magnetic Materials   233   Nov 2013   [Refereed]
Design of a Three-Terminal MTJ-Based Nonvolatile Logic Element with a 2-ns 64-Bit-Parallel Reconfiguration Capability
D. Suzuki, M. Natsui, A. Mochizuki, and T. Hanyu
Ext. Abstr. 2013 Int. Conf. Solid-State Devices and Materials   386-387   Sep 2013   [Refereed]
Fabrication of a 99%-Energy-Less Nonvolatile Multi-Functional CAM Chip Using Hierarchical Power Gating for a Massively-Parallel Full-Text-Search Engine
S. Matsunaga, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, T. Sugibayashi, S. Miura, H. Honjo, K. Kinoshita, H. Sato, S. Fukami, M. Natsui, A. Mochizuki, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu
2013 Symposium on VLSI Circuits Digest of Technical Papers   106-107   Jun 2013   [Refereed]
M. Natsui, N. Sakimura, T. Sugibayashi, and T. Hanyu
IEEE International Symposium on Circuits and Systems (ISCAS)   105-108   May 2013   [Refereed]
M. Natsui, K. Kashiuchi, and T. Hanyu
43rd IEEE International Symposium on Multiple-Valued Logic (ISMVL)   147-151   May 2013   [Refereed]
D. Suzuki, Y. Lin, M. Natsui, and T. Hanyu
Japanese Journal of Applied Physics   52(4) 04CM04-1-04CM04-6   Mar 2013   [Refereed]
M. Natsui, D. Suzuki, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, T. Sugibayashi, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu
2013 IEEE International Solid-State Circuits Conference (ISSCC)   194-195   Feb 2013   [Refereed]
Design of Process-Variation-Resilient Analog Basic Components Using Magnetic-Tunnel-Junction Devices
M. Natsui and T. Hanyu
Journal of Multiple-Valued Logic and Soft Computing   21(5-6) 597-608   2013   [Refereed]
D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, K. Kinoshita, H. Sato, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu
IEICE Electronics Express   10(23) 20130772   2013   [Refereed]
D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, K. Kinoshita, S. Fukamai, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu
Journal of Applied Physics   115(17) 17B742-1-17B742-3   2013   [Refereed]
Design of a Compact Nonvolatile Lookup-Table Circuit Using Three-Terminal Magnetic-Tunnel-Junction-Based Single-Ended Structure
D. Suzuki, Y. Lin, M. Natsui, and T. Hanyu
Ext. Abstr. Solid-State Devices and Materials (SSDM)   392-393   Sep 2012   [Refereed]
Daisuke Suzuki, Masanori Natsui, and Takahiro Hanyu
Proceedings of the 55th IEEE Midwest Symposium on Circuits and Systems (MWSCAS)   334-337   Aug 2012   [Refereed]
Masanori Natsui and Takahiro Hanyu
Proceedings of 10th IEEE International NEWCAS Conference   97-100   Jun 2012   [Refereed]
Masanori Natsui, Youngkeun Kim, and Takahiro Hanyu
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic   214-219   May 2012   [Refereed]
Youngkeun Kim, Masanori Natsui, and Takahiro Hanyu
International Symposium on Circuits and Systems (iscas2012)   2705-2708   May 2012   [Refereed]
Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
Journal of Applied Physics   111(7) 07E336-1-07E336-3   Apr 2012   [Refereed]
Daisuke Suzuki, Masanori Natsui, Tetsuo, Endoh, Hideo Ohno, and Takahiro Hanyu
Japanese Journal of Applied Physics   51(4) 04DM02-1-04DM02-5   Apr 2012   [Refereed]
Daisuke Suzuki, Masanori Natsui, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
Journal of Applied Physics   111(7) 07E318-1-07E318-3   Feb 2012   [Refereed]
Shoun Matsunaga, Masanori Natsui, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
The 17th Asia and South Pacific Design Automation Conference (ASP-DAC)   475-476   Feb 2012   [Refereed]
Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
Japanese Journal of Applied Physics   51(2) 02BM06-1-02BM06-5   Feb 2012   [Refereed]
Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique
Masanori Natsui, Takashi Arimitsu and Takahiro Hanyu
Journal of Multiple-Valued Logic and Soft Computing   19(1-3) 219-231   2012   [Refereed]
Design of a 270ps-Access 7T-2MTJ-Cell Nonvolatile Ternary Content-Addressable Memory
Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
56th Annual Conference on Magnetism and Magnetic Materials(MMM2011)   479-479   Nov 2011   [Refereed]
50%-Transistor-Less Standby-Power-Free 6-input LUT Circuit Using Redundant MTJ-Based Nonvolatile Logic-in-Memory Architecture
Daisuke Suzuki, Masanori Natsui, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
56th Annual Conference on Magnetism and Magnetic Materials(MMM2011)   480-480   Nov 2011   [Refereed]
MTJ-Based Optimal Vth-Tuning Technique for a Process-Variation-Aware VLSI processor
Masanori Natsui, Kim Yong Kun, and Takahiro Hanyu
56th Annual Conference on Magnetism and Magnetic Materials(MMM2011)   480-481   Nov 2011   [Refereed]
Evaluation of Vth-Variation Effect on Multiple-Valued Current-Mode Circuits
Kiyohiro Kashiuchi, Masanori Natsui, and Takahiro Hanyu
Japan-China-Korea Conference on Electronics & Communications 2011 (GWEI''11)   157-157   Oct 2011
A Compact Nonvolatile Logic Element Using an MTJ/MOS-Hybrid Structure
Daisuke Suzuki, Masanori Natsui, Hideo Ohno and Takahiro Hanyu
2011 International Conference on Solid State Devices and Materials (SSDM)   1464-1465   Sep 2011   [Refereed]
High-Speed-Search Nonvolatile TCAM Using MTJ Devices
Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
2011 International Conference on Solid State Devices and Materials (SSDM)   454-455   Sep 2011   [Refereed]
Shoun Matsunaga, Masanori Natsui, Shoji Ikeda, Katsuya Miura,Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
Japanese Journal of Applied Physics   50 063004-1-063004-7   Jun 2011   [Refereed]
Fully Parallel 6T-2MTJ Nonvolatile TCAM with Single-Transistor-Based Self Match-Line Discharge Control
Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Shunsuke Fukami,Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
2011 Symposium on VLSI Circuits, Digest of Technical Papers   298-299   Jun 2011   [Refereed]
Shoun Matsunaga, Akira Katsumata, Masanori Natsui and Takahiro Hanyu
Proc. 41st IEEE International Symposium on Multiple-Valued Logic   99-104   May 2011   [Refereed]
不揮発性ロジックインメモリアーキテクチャが拓く新概念VLSI設計パラダイム
夏井雅典,羽生貴弘
LSIとシステムのワークショップ2011   65-70   May 2011   [Invited]
Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology
T. Konishi, K. Inazu, J. G. LEE, M. Natsui, S. Masui and B. Murmann
IEICE Trans. on Electronics   E94-C(3) 334-345   Mar 2011   [Refereed]
不揮発性ロジックインメモリアーキテクチャが拓く新コンピューティングパラダイムの展望
夏井雅典,羽生貴弘
第58回 応用物理学関係連合講演会   78-78   Mar 2011   [Invited]
Design of a Process-Variation-Aware Nonvolatile MTJ-Based Lookup-Table Circuit
Daisuke Suzuki, Masanori Natsui, Hideo Ohno,and Takahiro Hanyu
2010 International Conference on Solid-State Devices and Materials, Workshop   1146-1147   Sep 2010   [Refereed]
Power-Aware Bit-Serial Binary Content-Addressable Memory Using Magnetic-Tunnel-Junction-Based Fine-Grained Power-Gating Scheme
Shoun Matsunaga, Masanori Natsui, Hideo Ohno, and Takahiro Hanyu
2010 International Conference on Solid-State Devices and Materials, Workshop   565-566   Sep 2010   [Refereed]
Hirokatsu Shirahama, Takashi Matsuura, Masanori Natsui, and Takahiro Hanyu
IEICE Trans. on Information and Systems   E93-D(8) 2080-2088   Aug 2010   [Refereed]
M. Natsui, T. Arimitsu and T. Hanyu
Proc. 40th IEEE International Symposium on Multiple-Valued Logic   235-240   May 2010   [Refereed]
Process-Variation-Aware VLSI Design Using an Emerging Functional Devices and Its Impact
M. Natsui and T. Hanyu
Booklet of the 19th International Workshop on Post-Binary ULSI Systems   20-25   May 2010
S. Matsunaga, M. Natsui, K. Hiyama, T. Endoh, H. Ohno and T. Hanyu
Japanese Journal of Applied Physics   49(2) 04DM05-1-04DM05-5   Apr 2010   [Refereed]
Fine-Grain Power-Gating Scheme of a CMOS/MTJ-Hybrid Bit-Serial Ternary Content-Addressable Memory
Shown Matsunaga, Atsushi Matsumoto, Masanori Natusi, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
Proc. of International Conference on Solid State Devices and Materials   1382-1383   Oct 2009   [Refereed]
MOS/MTJ-Hybrid Circuit with Nonvolatile Logic-in-Memory Architecture
Masanori Natsui and Takahiro Hanyu
Proc. of International Conference on Solid State Devices and Materials   1398-1399   Oct 2009   [Invited]
TMR ロジックに基づくルックアップテーブル回路とその瞬時復帰可能FPGA への応用
鈴木大輔, 夏井雅典, 羽生貴弘
電子情報通信学会論文誌C   J92-C(7) 233-240   Jul 2009   [Refereed][Invited]
Fabrication of a Nonvolatile Lookup-Table Circuit Chip Using Magneto/Semiconductor-Hybrid Structure for an Immediate-Power-Up Field Programmable Gate Array
Daisuke Suzuki, Masanori Natsui, Shoji Ikeda, Haruhiro Hasegawa, Katsuya Miura, Jun Hayakawa, Tetsuo Endoh, Hideo Ohno and Takahiro Hanyu
IEEE 2009 Symposia on VLSI Circuits, Dig. Tech. Papers   80-81   Jun 2009   [Refereed][Invited]
MTJ・CMOSハイブリッド回路に基づく低電力・高信頼LSI技術
夏井雅典, 羽生貴弘
LSIとシステムのワークショップ2009講演論文集   351-353   May 2009   [Invited]
Takashi Matsuura, Hirokatsu Shirahama, Masanori Natsui and Takahiro Hanyu
Proc. 39th IEEE International Symposium on Multiple-Valued Logic   60-65   May 2009   [Refereed][Invited]
GAを用いた演算増幅器の素子値最適化における主成分分析による探索効率の向上
竹原裕司, 夏井雅典, 田所嘉昭
システムLSI設計技術研究会   123-128   Jan 2009   [Invited]
Systematic Design and Verification of Binary/Multiple-Valued Fused Logic Circuits
Takashi Arimitsu, Tasuku Nagai, Masanori Natsui and Takahiro Hanyu
Proceedings of 2008 China-Korea-Japan Graduates Workshop on Electronic Information   178   Oct 2008   [Invited]
適応的電流源制御に基づくパイプライン電流モード多値演算回路の低電力化
松浦貴史,白濱弘勝,夏井雅典,羽生 貴弘
多値論理研究ノート   31 15-1-15-6   Sep 2008   [Invited]
次世代VLSI向き多値回路の系統的設計
夏井雅典,羽生貴弘
多値論理研究ノート   31 16-1-16-6   Sep 2008   [Invited]
主成分分析に基づく探索空間補正を用いた進化的素子値最適化システムと演算増幅器設計への応用
竹原裕司, 夏井雅典, 田所嘉昭
電子情報通信学会 2008ソサイエティ大会   A-3-1   Sep 2008   [Invited]
出力状態モニタリングに基づく電流モード多値順序回路の低消費電力化
松浦貴史, 白濱弘勝, 夏井雅典, 羽生貴弘
平成20年度電気関係学会東北支部連合大会講演論文集   (2J17) 369   Aug 2008   [Invited]
Automated Sizing of Analog Circuits based on Genetic Algorithm with Parameter Orthogonalization Procedure
M. Natsui, Y. Tadokoro
Proceedings of the Fifth International Conference on Informatics in Control, Automation and Robotics      May 2008   [Refereed]
GAを用いたオペアンプの最適素子値探索における個体表現の検討
竹原裕司, 夏井雅典, 田所嘉昭
電子回路研究会   ECT-08 41-46   Mar 2008   [Invited]
演算増幅器の進化的素子値最適化における個体表現の検討
竹原裕司, 夏井雅典, 田所嘉昭
電子情報通信学会 基礎・境界2008年総合大会   A-3-6   Mar 2008   [Invited]
並列構成共振型くし形フィルタによる打楽器音を含む楽音の音高推定法
田所嘉昭,寺井優,夏井雅典
平成19年度電気関係学会東海支部連合大会   O-184   Sep 2007   [Invited]
並列構成共振型くし形フィルタによる多和音の音高推定法
田所嘉昭,松山大仁郎,夏井雅典
平成19年度電気関係学会東海支部連合大会   O-185   Sep 2007   [Invited]
共振型・ノッチ型くし形フィルタによる広音域楽音の音高推定法
松下史也,夏井雅典,田所嘉昭
平成19年度電気関係学会東海支部連合大会   O-252   Sep 2007   [Invited]
主成分分析による遺伝的アルゴリズムの探索効率化と低電圧型カレントミラー回路のパラメータ最適化への応用
夏井雅典,田所嘉昭
平成19年度電気関係学会東海支部連合大会   O-177   Sep 2007   [Invited]
くし形フィルタに基づく自動採譜システムの実現
坂内秀幸, 夏井雅典, 田所嘉昭
第71回音楽情報科学研究会   2007-MUS-071 13-18   Aug 2007   [Invited]
7段縦続接続くし形フィルタによるピアノ和音の音高推定法の検討
松山大仁郎, 夏井雅典, 田所嘉昭
第71回音楽情報科学研究会   2007-MUS-071 167-172   Aug 2007   [Invited]
並列構成くし形フィルタによる広音域ピアノ楽音の音高推定法
松下史也, 夏井雅典, 田所嘉昭
第71回音楽情報科学研究会   2007-MUS-071 173-178   Aug 2007   [Invited]
GAを用いたオペアンプの最適パラメータ探索に関する一検討
竹原裕司,夏井雅典,田所嘉昭
電子回路研究会   ECT-07 19-24   Jun 2007   [Invited]

Misc

 
スピンを用いた不揮発ロジックの展望
羽生 貴弘,夏井 雅典
技術総合誌 OHM   (1) 28-30   Jan 2012

Books etc

 
Informatics in Control Automation and Robotics : Selected Papers from the International Conference on Informatics in Control Automation and Robotics 2006
J. Andrade-Cetto, J-L. Ferrier, J. D. Pereira, J. Filipe (EDT). (Part:Joint Editor, pp.327-338)
Springer   Feb 2008   ISBN:9783540791416
Introduction to Magnetic Random-Access Memory
Takahiro Hanyu, Tetsuo Endoh, Shoji Ikeda, Tadahiko Sugibayashi, Naoki Kasai, Daisuke Suzuki, Masanori Natsui, Hiroki Koike, and Hideo Ohno (Part:Joint Work, Chapter 7: Beyond MRAM: Nonvolatile Logic-in-Memory VLSI)
Wiley-IEEE Press   Dec 2016   ISBN:978-1-119-00974-0

Conference Activities & Talks

 
脳型LSIを拓く集積回路・アーキテクチャの展望
夏井雅典
VLSI夏の学校「LSI技術者のための人工知能基礎講座」   25 Aug 2018   
脳型計算に基づく非シグネチャ不正侵入検出手法
須田拓樹,夏井雅典,羽生貴弘
信学会第2種研究会「多値論理とその応用」   6 Jan 2018   
時系列特徴を用いたチップ内データ転送エラー訂正手法とその可能性
加藤健太郎,夏井雅典,羽生貴弘
デザインガイア2017   6 Nov 2017   
時系列特徴を用いた脳型計算ベース車載ネットワークセキュリティ技術
夏井雅典,須田拓樹,羽生貴弘
第40回多値論理フォーラム   16 Sep 2017   
脳型計算に基づく車載ネットワークの不正侵入検出法
須田拓樹, 夏井雅典, 羽生貴弘
平成29年度 電気関係学会東北支部連合大会   24 Aug 2017   

Research Grants & Projects

 
スピントロニクス技術を活用した分散型ITシステム向け回路・アーキテクチャ技術
Project Year: Oct 2014 - Today
新概念脳型LSI設計技術に関する研究
Project Year: Apr 2014 - Today
アナログ回路設計支援技術に関する研究
Project Year: Apr 2000 - Today
脳型コンピューティング向けダーク・シリコンロジックLSIの基盤技術開発
科学研究費補助金
Project Year: Apr 2016 - Mar 2021    Investigator(s): Takahiro Hanyu
知的環境適応型VLSI基盤技術の構築と高信頼脳型LSIシステムへの応用展開
Grant-in-Aid for Scientific Research
Project Year: Oct 2017 - Mar 2020
完全自律誤り訂正VLSI設計技術の構築と脳型LSIシステムへの応用展開
科学研究費補助金
Project Year: Apr 2016 - Mar 2019    Investigator(s): NATSUI Masanori
脳の知的情報処理ダイナミクスを活用した高性能・高信頼エレクトロニクスシステムの研究開発技術開発
村田学術振興財団: 平成28年度助成研究
Project Year: Jul 2016 - Jun 2017    Investigator(s): NATSUI Masanori
不揮発性素子を用いたPVTバラつきフリーVLSIシステムに関する研究
Grant-in-Aid for Scientific Research
Project Year: Apr 2010 - Mar 2014
製造ばらつきフリー高信頼多値VLSIの系統的設計技術に関する研究
Grant-in-Aid for Scientific Research
Project Year: Apr 2009 - Mar 2012
楽音の解析とそのIT社会への応用に関する研究
科学研究費補助金
Project Year: Apr 2007 - Mar 2008    Investigator(s): 田所 嘉昭

Patents

 
特開2008-052023 : 多和音の音名と音高推定手法
田所嘉昭,夏井雅典,松山大仁郎

Others

 
Jul 2016   脳の知的情報処理ダイナミクスを活用した高性能・高信頼エレクトロニクスシステムの研究開発
人間の脳は「過去の経験や記憶に基づく予測制御的な情報の補完あるいは訂正」という極めて高度な処理を日常的に行っている.本研究では,超微細半導体素子および次世代素子の性能向上を最大限に活用可能な計算機アーキテクチャの構築に向け,脳の知的情報処理ダイナミクスを活用した高精度・高効率・高信頼データ処理技術の確立を目的とする.過去の時系列データの時間的相関関係や内包される本質的特徴を創発的に獲得し,未来に到来するデータの予測やエラー訂正を可能とする計算アルゴリズム,および本アルゴリズムを高効率かつコンパクトに実装する計算機アーキテクチャ基盤技術の確立により,情報の冗長化を基本とする従来手法とは一線を画するエラー耐性および転送効率を達成するデータ処理技術,および本技術を内包した高信頼ハードウェアアーキテクチャの実現を目指す.