論文

査読有り
1990年

Logic design system with evaluation‐redesign mechanism

Electronics and Communications in Japan (Part III: Fundamental Electronic Science)
  • Fumihiro Maruyama
  • ,
  • Taeko Kakuda
  • ,
  • Yusuke Matsunaga
  • ,
  • Nobuaki Kawato
  • ,
  • Yoriko Minoda
  • ,
  • Shuho Sawada

73
5
開始ページ
105
終了ページ
113
記述言語
英語
掲載種別
研究論文(学術雑誌)
DOI
10.1002/ecjc.4430730511

Sophisticated CAD (Computer‐Aided Design) systems that can produce quality designs quickly are anticipated to keep pace with the remarkable advance of VLSI technology. This paper presents a cooperative logic design system, co‐LODEX, in the two streams of design, datapath design and control design. The feature of co‐LODEX is its evaluation‐redesign mechanism using assumption‐based reasoning, which automates the evaluate‐redesign cycle under constraints. As constraints co‐LODEX takes those on area and speed. Design alternatives are considered as assumptions and constraint violations as contradictions. Redesign was implemented as contraction resolution. Here, justifications are defined for constraint violations whose forms are independent of actual constraint values, and the evaluation‐redesign mechanism based on these justifications is described. An experimental system was implemented and it was observed that it could correctly carry out the evaluation‐redesign mechanism. It enables the user to specify constraints in terms of numbers and obtain a circuit satisfying all of them. It also allows the user to obtain a variety of circuits efficiently with different characteristics conforming to the same specification by changing constraints. Copyright © 1990 Wiley Periodicals, Inc., A Wiley Company

リンク情報
DOI
https://doi.org/10.1002/ecjc.4430730511
ID情報
  • DOI : 10.1002/ecjc.4430730511
  • ISSN : 1520-6440
  • ISSN : 1042-0967
  • SCOPUS ID : 0025424940

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