宮瀬紘平 (Kouhei Miyase) - マイポータル

基本情報

所属: 九州工業大学大学院情報工学研究院情報・通信工学研究系准教授

学位: 博士（情報工学）(九州工業大学)

研究者番号: 30452824
J-GLOBAL ID: 201001009936362873
researchmap会員ID: 6000023877

研究分野

MISC

112

Scan chain grouping for mitigating ir-drop-induced test data corruption

Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian

Proceedings of the Asian Test Symposium 140-145 2018年1月24日
Scan chain grouping for mitigating ir-drop-induced test data corruption

Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian

Proceedings of the Asian Test Symposium 140-145 2018年1月24日
Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory

Lu S, Li H, Miyase K

2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, IOLTS 2018 226-227 2018年
Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory

226-227 2018年
Analysis and mitigation or IR-Drop induced scan shift-errors

Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen

Proceedings - International Test Conference 2017- 1-8 2017年12月29日
Analysis and mitigation or IR-Drop induced scan shift-errors

Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen

Proceedings - International Test Conference 2017- 1-8 2017年12月29日
Locating Hot Spot with Justification Techniques in a Layout Design

K. Miyase, Y. Kawano, X. Wen, S. Kajihara

IEEE Workshop on RTL and High Level Testing 2017年
Locating Hot Spot with Justification Techniques in a Layout Design

K. Miyase, Y. Kawano, X. Wen, S. Kajihara

IEEE Workshop on RTL and High Level Testing 2017年
Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation

Fuqiang Li, Xiaoqing Wen, Kohei Miyase, Stefan Holst, Seiji Kajihara

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E99A(12) 2310-2319 2016年12月
Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation

Fuqiang Li, Xiaoqing Wen, Kohei Miyase, Stefan Holst, Seiji Kajihara

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E99A(12) 2310-2319 2016年12月
On Optimal Power-aware Path Sensitization

Matthias Sauer, Jie Jiang, Sven Reimer, Kohei Miyase, Xiaoqing Wen, Bernd Becker, Ilia Polian

2016 IEEE 25TH ASIAN TEST SYMPOSIUM (ATS) 179-184 2016年
Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test

Stephan Eggersgluess, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen

2016 IEEE 25TH ASIAN TEST SYMPOSIUM (ATS) 173-178 2016年
SAT-Based Post-Processing for Regional Capture Power Reduction in At-Speed Scan Test Generation （共著）

Stephan Eggersgluss, Kohei Miyase, Xiaoqing Wen

European Test Symposium 2016年
On Optimal Power-aware Path Sensitization

Matthias Sauer, Jie Jiang, Sven Reimer, Kohei Miyase, Xiaoqing Wen, Bernd Becker, Ilia Polian

2016 IEEE 25TH ASIAN TEST SYMPOSIUM (ATS) 179-184 2016年
Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test

Stephan Eggersgluess, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen

2016 IEEE 25TH ASIAN TEST SYMPOSIUM (ATS) 173-178 2016年
SAT-Based Post-Processing for Regional Capture Power Reduction in At-Speed Scan Test Generation "jointly worked"

Stephan Eggersgluss, Kohei Miyase, Xiaoqing Wen

European Test Symposium 2016年
Logic/Clock-Path-Aware AtSpeed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch (共著)

Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael A. Kochte, Eric Schneider, Hans‐Joachim Wunderlich, Jun Qian

Proc. Asian Test Symposium 1-6 2015年
Identification of High Power Consuming Areas with Gate Type and Logic Level Information (共著)

Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara

Proc. European Test Symposium 1-6 2015年
A Soft-Error Tolerant TCAM Using Partial Don't-Care Keys （共著）

Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen, Stefan Holst, Kohei Miyase

European Test Symposium 2015年
Logic/Clock-Path-Aware AtSpeed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch "jointly worked"

Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jun Qian

Proc. Asian Test Symposium 1-6 2015年

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