2019年1月16日
14ns write speed 128Mb density Embedded STT-MRAM with endurance>10 10 and 10yrs retention@85°C using novel low damage MTJ integration process
Technical Digest - International Electron Devices Meeting, IEDM
- 巻
- 2018-December
- 号
- 開始ページ
- 27.2.1
- 終了ページ
- 27.2.4
- 記述言語
- 掲載種別
- 研究論文(国際会議プロシーディングス)
- DOI
- 10.1109/IEDM.2018.8614606
© 2018 IEEE. Novel damage control integration process technology has been developed through development of new low-damage MgO deposition process, low-damage RIE process, and low temperature SiN-cap process. Application of the developed damage control integration process technology to MTJ fabrication enabled us to demonstrate an improvement of TMR ratio, thermal stability factor, and switching efficiency. Moreover, it is shown that the endurance of the fabricated MTJs is over 10 10 , although thermal stability factor drastically increased. Finally, with the developed 37-nm p-MTJ technology and the damage control integration process technology, 128Mb density embedded STT-MRAM was fabricated. By using our 128Mb density STT-MRAM, 14ns write speed at V dd of 1.2V was successfully demonstrated. This result will contribute to low power MCU/IoT chip solution and so on.
- リンク情報
- ID情報
-
- DOI : 10.1109/IEDM.2018.8614606
- ISSN : 0163-1918
- SCOPUS ID : 85061808243