MISC

2000年5月

Dynamically variable line-size cache architecture for merged DRAM/Logic LSIs

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
  • K Inoue
  • ,
  • K Kai
  • ,
  • K Murakami

E83D
5
開始ページ
1048
終了ページ
1057
記述言語
英語
掲載種別
出版者・発行元
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called "dynamically variable line-size cache (D-VLS cache)." The D-VLS cache ran optimize its line-size according to the characteristic of programs, and attempts to improve the performance by exploiting the high on-chip memory bandwidth on merged DRAM/logic LSIs appropriately. In our evaluation, it is observed that an average memory access time improvement achieved by a direct-mapped D-VLS cache is about 20% compared to a conventional direct-mapped cache with tired 32-byte lines. This performance improvement is better than that of a doubled-size conventional direct-mapped cache*.

Web of Science ® 被引用回数 : 1

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Web of Science
https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:000087317800013&DestApp=WOS_CPL

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