- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called "dynamically variable line-size cache (D-VLS cache)." The D-VLS cache ran optimize its line-size according to the characteristic of programs, and attempts to improve the performance by exploiting the high on-chip memory bandwidth on merged DRAM/logic LSIs appropriately. In our evaluation, it is observed that an average memory access time improvement achieved by a direct-mapped D-VLS cache is about 20% compared to a conventional direct-mapped cache with tired 32-byte lines. This performance improvement is better than that of a doubled-size conventional direct-mapped cache*.
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