MISC

2000年11月

A high-performance/low-power on-chip memory-path architecture with variable cache-line size

IEICE TRANSACTIONS ON ELECTRONICS
  • K Inoue
  • ,
  • K Kai
  • ,
  • K Murakami

E83C
11
開始ページ
1716
終了ページ
1723
記述言語
英語
掲載種別
出版者・発行元
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size (D-VLS) cache for high performance and low energy consumption. The D-VLS cache exploits the high on-chip memory bandwidth attainable on merged DRAM/logic LSIs by replacing a whole large cache line in one cycle. At the same time, it attempts to avoid frequent evictions by decreasing the cache-line size when programs have poor spatial locality. Activating only on-chip DRAM subarrays corresponding to a replaced cache-line size produces a significant energy reduction. Ln our simulation, it is observed that our proposed on-chip memory-path architecture, which employs a direct-mapped D-VLS cache, improves the ED (Energy Delay) product by more than 75% over a conventional memory-path model.

Web of Science ® 被引用回数 : 2

リンク情報
Web of Science
https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:000165580700004&DestApp=WOS_CPL

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