論文

査読有り
2002年2月

Omitting cache look-up for high-performance, low-power microprocessors

IEICE TRANSACTIONS ON ELECTRONICS
  • K Inoue
  • ,
  • VG Moshnyaga
  • ,
  • K Murakami

E85C
2
開始ページ
279
終了ページ
287
記述言語
英語
掲載種別
研究論文(学術雑誌)
出版者・発行元
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

In this paper, we propose a novel architecture for low-power direct-mapped instruction caches, called "history-based tag-comparison (HBTC) cache." The cache attempts to reuse tag-comparison results for avoiding unnecessary tag checks. Execution footprints are recorded into an extended BTB (Branch Target Buffer). In our evaluation, it is observed that the energy for tag comparison can be reduced by more than 90% in many applications.


リンク情報
Web of Science
https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:000173951100007&DestApp=WOS_CPL

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