Feb, 2002
Omitting cache look-up for high-performance, low-power microprocessors
IEICE TRANSACTIONS ON ELECTRONICS
- ,
- ,
- Volume
- E85C
- Number
- 2
- First page
- 279
- Last page
- 287
- Language
- English
- Publishing type
- Research paper (scientific journal)
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
In this paper, we propose a novel architecture for low-power direct-mapped instruction caches, called "history-based tag-comparison (HBTC) cache." The cache attempts to reuse tag-comparison results for avoiding unnecessary tag checks. Execution footprints are recorded into an extended BTB (Branch Target Buffer). In our evaluation, it is observed that the energy for tag comparison can be reduced by more than 90% in many applications.
- Link information
- ID information
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- ISSN : 1745-1353
- Web of Science ID : WOS:000173951100007