Amano, Hideharu

J-GLOBAL         Last updated: May 29, 2019 at 03:59
 
Avatar
Name
Amano, Hideharu
URL
http://www.am.ics.keio.ac.jp/
Affiliation
Keio University
Section
Faculty of Science and Technology Department of Information and Computer Science
Job title
Professor
Degree
工学 (Keio University)
Research funding number
60175932

Research Areas

 
 

Academic & Professional Experience

 
Apr 1985
 - 
Mar 1989
大学助手(理工学部電気工学科)
 
Apr 1989
 - 
Mar 1994
大学専任講師(理工学部電気工学科)
 
Oct 1989
 - 
Sep 1990
Stanford大学 ,訪問講師
 
Apr 1994
 - 
Mar 1996
大学助教授(理工学部電気工学科)
 
Apr 1996
 - 
Mar 2001
大学助教授(理工学部情報工学科)
 

Education

 
Mar 1981
   
 
電気工学科, Faculty of Engineering, Keio University
 
Mar 1983
   
 
電気工学専攻, Graduate School, Division of Engineering, Keio University
 
Mar 1986
   
 
電気工学専攻, Graduate School, Division of Engineering, Keio University
 

Committee Memberships

 
Oct 2015
 - 
Today
IEEE/ACM International Symposium on Networks on Chip (NOCS) 2016  General Chair
 
May 2015
 - 
Today
電子情報通信学会、情報処理学会  FIT実行委員長
 
May 2015
 - 
Today
電子情報通信学会  ISS副会長
 
May 2015
 - 
Mar 2016
情報処理学会  全国大会プログラム委員長
 
May 2011
 - 
May 2013
電子情報通信学会コンピュータシステム研究専門委員会  専門委員長
 

Awards & Honors

 
Sep 2015
電子情報通信学会フェロー
 
May 2014
ISS功績賞, 電子情報通信学会
 
May 2008
Network-on-ChipにおけるFat H-Treeトポロジに関する研究, Best Paper Award, IPSJ
Winner: 松谷、鯉渕、天野
 
May 2003
Implementing of a Virtual Hardware on DRL, Best Paper Award, IEICE
Winner: 柴田、宇野、天野
 
1997
情報処理学会坂井記念学術賞, 情報処理学会
Winner: 天野 英晴
 

Published Papers

 
Accelerator-in-Switch: a framework for tightly couple switching hub and an accelerator with FPGA
Chiharu Tsuruta, Takahiro Kaneda, Naoki Nishikawa, Hideharu Amano
International Conference on Filed Programmable Logic and Applications      Sep 2018   [Refereed]
Implementation of Bitsliced AES Encryption on CUDA-Enabled GPU
Naoki Nishikawa, Hideharu Amano, Keisuke Iwai
International Conference on Network and System Security      Aug 2018   [Refereed]
Hayate Okuhara, A.Ben Arhmed , J.M.Muehn, Hideharu Amano
IEEE Transactions on VLSI Systems      Aug 2018
Okuhara Hayate, Ben Ahmed Akram, Hideharu Amano
IEEE Transactions on Circuits and Systems I: Regular Papers      Aug 2018   [Refereed]
Body Biasを用いてディジタルシステムの性能を自動チューニングする方法の提案
Optimization of Body Biasing for Variable Pipelined Coarse Grained Reconfigurable Architecture
Takuya Kojima, Naoki Ando, Anh Vu Doan, Hideharu Amano
IEICE Transactions on Information and Systems   E10-D(6)    Aug 2018   [Refereed]
CGRAの電力最適化をパイプライン構造の最適化により実現する

Books etc

 
FPGAの原理と構成
AMANO HIDEHARU (Part:Editor)
オーム社   Apr 2016   
ディジタル回路設計とコンピュータアーキテクチャ ARM版
AMANO HIDEHARU (Part:Joint Translation)
SiBアクセス   Apr 2016   
Computer Architecture, A Quantitative Approach
J.L.Hennessy and D.A.Patterson (Part:Joint Translation)
翔泳社   Mar 2014   
CMOS VLSI Design
N.H.E.Weste, D.M.Harris (Part:Joint Translation, 10章、付録)
丸善出版   Jan 2014   
マンガでわかるディジタル回路
AMANO HIDEHARU (Part:Joint Work)
オーム社   Dec 2013   

Conference Activities & Talks

 
Zynq Cluster for CFD Parametric Survey
AMANO HIDEHARU
the International Symposium on Applied Reconfigurable Computing (ARC)   Feb 2016   
Randomizing Packet Memory Networks for Low-latency Processor-memory Communication
AMANO HIDEHARU
The 24th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)   Feb 2016   IEEE
Power Optimization considering the chip temperature of low power reconfigurable accelerator CMA-SOTB
AMANO HIDEHARU
he 4rd International Symposium on Computing and Networking (CANDAR)   Dec 2015   IEICE
A 297MOPS/0.4mW Ultra Low Power Coarse-grained Reconfigurable Accelerator CMA-SOTB-2
AMANO HIDEHARU
The 10th International Conference on ReConFigurable Computing and FPGAs   Dec 2015   
On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck
AMANO HIDEHARU
the 9th ACM/IEEE International Symposium on Networks-on-Chip (NOCS)   Oct 2015   

Research Grants & Projects

 
Stacking methods with chip bridges for a building block computing system
MEXT,JSPS: Grant-in-Aid for Scientific Research
Project Year: Apr 2018 - Mar 2021    Investigator(s): 天野 英晴
A Study on Building-Block Computing Systems using Inductive Coupling Interconnect
MEXT,JSPS: Grant-in-Aid for Scientific Research
Project Year: May 2013 - Mar 2018    Investigator(s): 天野 英晴

Social Contribution

 
ASP Design Automation Conference 2000
[]  1998 - Today
Cool Chips 1999
[]  1998 - Today
Japanese FPGA/PLD Conference and Exhibit
[]  1998 - Today
ASP Design Automation Conference 1998
[]  1997 - Today
IASTED International Conference of Applied Informa
[]  1997 - 1998