Takahiro Hanyu

Profile Information

Affiliation: Professor, Research Institute of Electrical Communication, System & Software Division, New Paradigm VLSI System, Tohoku University

Degree: Ph. D(Mar, 1989, Tohoku University)

J-GLOBAL ID: 200901015971474624
researchmap Member ID: 1000004954

External link: https://www.riec.tohoku.ac.jp/en/organization/section4/vlsi/

Research Interests

Research Areas

Awards

May, 2018

Excellent Young Researcher Presentation Award, Technical Committee on Integrated Circuits and Devices (ICD), IEICE

Kentaro Kato, Masanori Natsui, Takahiro Hanyu
Apr, 2015

The Commendation for Science and Technology, "Study of Nonvolatile Logic-in-Memory Integrated Circuits", MEXT

Takahiro Hanyu
May, 2014

Best Paper Award Finalist, "A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure", IEEE ASYNC 2014

Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu
Sep, 2012

Paper Award, "High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction", SSDM 2012

Takashi Ohsawa, Fumitake Iga, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, and Tetsuo Endoh
Jul, 2010

Best Paper Award, "Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model", IEEE ISVLSI 2010

Naoya Onizawa, Tomoyoshi Funazaki, Takahiro Hanyu
May, 2010

Excellent Paper Award, "Design of a Lookup Table Circuit Based on TMR Logic and Its Application to an Immediate Wake-Upable FPGA", The Institute of Electronics, Information and Communication Engineers

Daisuke Suzuki, Masanori Natsui, Takahiro Hanyu
Apr, 2010

Ichimura Academic Award, "Development of Nonvolatile Logic-in-Memory Integrated Circuits"

Takahiro Hanyu
Sep, 2009

Excellent Paper Award (JJAP Paper Award), "Standby-Power-Free Compact Ternary Content-Addressable Memory Cell Chip Using Magnetic Tunnel Junction Devices", The Japan Society of Applied Physics

Shoun Matsunaga, Kimiyuki Hiyama, Atsushi Matsumoto, Shoji Ikeda, Haruhiro Hasegawa, Katsuya Miura, Jun Hayakawa, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Jan, 2007

University LSI Design Contest Special Feature Award, "Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic", ASP-DAC 2007

Shoun Matsunaga, Takahiro Hanyu, Hiromitsu Kimura, Takashi Nakamura, Hidemi Takasu
Nov, 2002

優秀ポスター賞, "Design of Low-Power Logic-in-Memory VLSI Using Ferroelectric Devices", 2002年システムLSIワークショップ

亀山充隆, 羽生貴弘, 木村啓明, 藤森敬和, 中村孝, 高須秀視
Jun, 2002

審査員特別賞, 強誘電体デバイスを用いたシステムLSI構築技術, 2002年度(第９回)ＬＳＩデザイン・オブ・ザ・イヤー

亀山充隆, 羽生貴弘, 木村啓明, 藤森敬和, 中村孝, 高須秀視
May, 2000

坂井記念特別賞, "Multiple-Valued Logic-in-Memory VLSI Based on Floating-Gate MOS Pass-Transistor Logic", （社）情報処理学会

羽生貴弘
May, 1988

Distinctive Contribution Award, "Quaternary Gate Array for Pattern Matching and its Application to Knowledge Information Processing System", IEEE ISMVL

Takahiro Hanyu, Michitaka Kameyama, Tatsuo Higuchi
Feb, 1988

丹羽記念賞, "Design and Implementation of an nMOS Image Processor Based on Quaternary Logic", 丹羽記念会

Takahiro Hanyu, Michitaka Kameyama, Tatsuo Higuchi
May, 1986

Award for Excellence, "Implementation of Quaternary NMOS Integrated Circuits for Pipelined Image Processing", IEEE ISMVL

Michitaka Kameyama, Takahiro Hanyu, Masayoshi Esashi, Tatsuo Higuchi, Takayasu Ito

Papers

524

Enhanced convergence in p-bit based simulated annealing with partial deactivation for large-scale combinatorial optimization problems

Naoya Onizawa, Takahiro Hanyu

Scientific Reports, 14(1), Jan 16, 2024
Stochastic Implementation of Simulated Quantum Annealing on PYNQ

Taiga Kubuta, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

2023 International Conference on Field Programmable Technology (ICFPT), Dec 12, 2023
Improving Stochastic Quantum-Like Annealing Based on Rerandomization

Ryoma Sasaki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec 4, 2023
Design of a nonvolatile-register-embedded RISC-V CPU with software-controlled data-retention and hardware-acceleration functions

Masanori Natsui, Keisuke Sakamoto, Takahiro Hanyu

Memories - Materials, Devices, Circuits and Systems, 4 100035-100035, Jul, 2023
Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing

Naoya Onizawa, Kyo Kuroki, Duckgyu Shin, Takahiro Hanyu

IEEE Open Journal of Signal Processing, 1-11, 2023
Self-Adaptive Gate Control for Efficient Escape from Local Minimum Energy on Invertible Logic

Naoya Onizawa, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu

IEEE Access, 11 1-1, 2023
Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing

Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu

IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 13(1) 1-1, 2023
Fast Solving Complete 2000-Node Optimization Using Stochastic-Computing Simulated Annealing

Kota Katsuki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Oct 24, 2022
Dynamic activation of power-gating-switch configuration for highly reliable nonvolatile large-scale integrated circuits

Fangcen Zhong, Masanori Natsui, Takahiro Hanyu

JAPANESE JOURNAL OF APPLIED PHYSICS, 61(SC), May, 2022
CMOS Invertible Logic: Bidirectional operation based on the probabilistic device model and stochastic computing

Naoya Onizawa, Takahiro Hanyu

IEEE Nanotechnology Magazine, 16(1) 33-46, Feb, 2022
Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing

Naoya Onizawa, Kota Katsuki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu

IEEE Transactions on Neural Networks and Learning Systems, 1-7, 2022
Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices

Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu

2021 IEEE Workshop on Signal Processing Systems (SiPS), Oct, 2021
High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians

Naoya Onizawa, Takahiro Hanyu

2021 IEEE International Symposium on Circuits and Systems (ISCAS), May, 2021
Design of a highly reliable nonvolatile flip-flop incorporating a common-mode write error detection capability

Masanori Natsui, Gensei Yamagishi, Takahiro Hanyu

Japanese Journal of Applied Physics, 60(SB) SBBB02-SBBB02, May 1, 2021
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under Field-Assistance-Free Condition

Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka …

IEEE Journal of Solid-State Circuits, 56(4) 1116-1128, Apr, 2021
Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices

Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu

IEEE Open Journal of Circuits and Systems, 2 782-791, 2021
Sparse Random Signals for Fast Convergence on Invertible Logic

Naoya Onizawa, Makoto Kato, Hitoshi Yamagata, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu

IEEE Access, 9 62890-62898, 2021
Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN

Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, Takahiro Hanyu

IEEE Transactions on Circuits and Systems I: Regular Papers, 68(1) 67-76, Jan, 2021
Memristive Computational Memory Using Memristor Overwrite Logic (MOL)

Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah, Naoya Onizawa, Takahiro Hanyu

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(11) 2370-2382, Nov, 2020
High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter

Naoya Onizawa, Shogo Mukaida, Akira Tamakoshi, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(10) 2171-2181, Oct, 2020

Misc.

129

New-Paradigm Logic-LSI Design Technology Based on Nonvolatile Storage Functionality and Its Future Prospects

夏井雅典, 羽生貴弘

電子情報通信学会論文誌 C(Web), J104-C(6), 2021
パワーゲーティング機能付き不揮発RISC-V CPUの基礎検討

坂本佳介, 夏井雅典, 羽生貴弘

電気関係学会東北支部連合大会講演論文集(CD-ROM), 2021, 2021
Operating-Condition-Aware Power-Gating-Switch Control Technique and Its Application to Nonvolatile Logic LSI

ZHONG Fangcen, ZHONG Fangcen, 夏井雅典, 羽生貴弘

電子情報通信学会技術研究報告(Web), 121(277(VLD2021 17-48)), 2021
Power-Gating Switch-Control Technique for Nonvolatile Logic LSI

ZHONG Fangcen, 夏井雅典, 羽生貴弘

電子情報通信学会技術研究報告(Web), 120(234(VLD2020 11-38)), 2020
非相補抵抗状態検出機能を有する高信頼MTJベース不揮発性フリップフロップの構成

山岸源征, 夏井雅典, 羽生貴弘

電気関係学会東北支部連合大会講演論文集(CD-ROM), 2019, 2019
省エネルギー二値化ニューラルネットワーク向けMTJベース積和演算回路の構成

千葉智貴, 夏井雅典, 羽生貴弘

電子情報通信学会技術研究報告, 119(284(ICD2019 28-43)), 2019
次世代IoT社会に向けた脳型LSI設計技術

夏井雅典, 羽生貴弘

電子情報通信学会大会講演論文集(CD-ROM), 2018, 2018
不揮発量子化ニューラルネットワーク構成に基づく小型・超低消費電力XNOR回路の構成

千葉智貴, 夏井雅典, 羽生貴弘

電気関係学会東北支部連合大会講演論文集(CD-ROM), 2018, 2018
Prospects of an Error-Correction Technique of Intra-Chip Data Transmission Using Time-Series Feature

117(277) 33-38, Nov 6, 2017
Special Section on Multiple-Valued Logic and VLSI Computing FOREWORD

Takahiro Hanyu

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E100D(8) 1555-1555, Aug, 2017
Spintronics Materials and Devices for Working Memory Technology FOREWORD

Hideo Ohno, Masafumi Yamamoto, Tetsuo Endoh, Yasuo Ando, Takahiro Hanyu, Kohei M. Itoh, Masaaki Tanaka, Seiji Mitani, Hitoshi Wakabayashi

JAPANESE JOURNAL OF APPLIED PHYSICS, 56(8), Aug, 2017
MTJ/MOSハイブリッド回路技術

Takahiro Hanyu

応用物理学会誌, 86(8) 662-665, Aug, 2017
ストカスティック演算に基づく省エネルギー脳型LSI設計技術

N. Onizawa, K. Matsumiya, T. Hanyu

IEICE Fundamental Review, 11(1) 28-39, Jul, 2017
Stochastic Computation for Energy-Efficient Brainware LSI

30 202-207, May 11, 2017
Measurement of Magnitude Response of FIR Filters Based on Stochastic Computation

30 38-40, May 11, 2017
On Measurement Methods of Frequency Magnitude Responses for Digital Filters Based on Stochastic Computation

2017(19) 1-6, Mar 13, 2017
視覚的注意計算モデルのハードウェア実装に向けた基礎的考察

西野海斗, 鬼沢直哉, 松宮一道, 塩入論, 羽生貴弘

電気関係学会東北支部連合大会講演論文集(CD-ROM), 2017, 2017
Design of High-Speed Low-Power Analog-to-Digital Converter for a Nonvolatile Micro-controller : High-Speed Low-Power Reference-Less SAR-ADC

116(334) 51-56, Nov 29, 2016
Hardware Implementation of Stochastic Gammatone Filter

116(95) 29-34, Jun 16, 2016
C-12-34 A Self-Terminated MTJ Write Driver and Its Application to a Random Number Generator

Suzuki Daisuke, Hanyu Takahiro

Proceedings of the IEICE General Conference, 2016(2) 107-107, Mar 1, 2016

Books and Other Publications

Introduction to Magnetic Random-Access Memory

Takahiro Hanyu, Tetsuo Endoh, Shoji Ikeda, Tadahiko Sugibayashi, Naoki Kasai, Daisuke Suzuki, Masanori Natsui, Hiroki Koike, Hideo Ohno (Role: Joint author, Chapter 7: Beyond MRAM: Nonvolatile Logic-in-Memory VLSI)

Wiley-IEEE Press, Dec, 2016 (ISBN: 9781119009740)
Spintronics-based Computing

T. Hanyu (Role: Joint author, Chapter 5: Challenge of Nonvolatile Logic LSI Using MTJ-Based Logic-in-Memory Architecture)

Springer, 2015 (ISBN: 9783319151793)
VLSI 2010 Annual Symposium: Selected Papers (Lecture Notes in Electrical Engineering)

N. Onizawa, F. Funazaki, A. Matsumoto, T. Hanyu (Role: Joint editor, 2章全部)

Springer-Verlag, Sep 7, 2011 (ISBN: 9400714874)
半導体ストレージ2012

羽生貴弘, 池田正二, 杉林直彦, 笠井直紀, 遠藤哲郎, 大野英男 (Role: Editor, 第3章ストレージ・クラス・メモリ（新型不揮発メモリ）「不揮発性ロジック：スピントロニクス素子を用いた待機電力ゼロのLSI技術を提案」)

日経BP社, Jul 29, 2011 (ISBN: 9784822265588)

Presentations

不揮発FPGAを用いた脳型情報処理アクセラレータの構成

鈴木大輔, 羽生貴弘

信学会第２種研究会「多値論理とその応用」, Jan 6, 2018
脳型計算に基づく非シグネチャ不正侵入検出手法

須田拓樹, 夏井雅典, 羽生貴弘

信学会第２種研究会「多値論理とその応用」, Jan 6, 2018
複数個の電圧電流変換特性を用いた低電力MTJベース真性乱数生成器の設計

向田渉吾, 鬼沢直哉, 羽生貴弘

信学会第２種研究会「多値論理とその応用」, Jan 6, 2018
Contextual Cueing Model に基づく実時間画像認識プリプロセッサの検討

西野海斗, 鬼沢直哉, 袁正雄, 松宮一道, 塩入諭, 羽生貴弘

信学会第２種研究会「多値論理とその応用」, Jan 6, 2018
時系列特徴を用いたチップ内データ転送エラー訂正手法とその可能性

加藤健太郎, 夏井雅典, 羽生貴弘

デザインガイア2017, Nov 6, 2017
時系列特徴を用いた脳型計算ベース車載ネットワークセキュリティ技術

夏井雅典, 須田拓樹, 羽生貴弘

第40回多値論理フォーラム, Sep 16, 2017
MTJベース多機能Lookup Table 回路の設計

鈴木大輔, 羽生貴弘

第40回多値論理フォーラム, Sep 16, 2017
ストカスティック演算に基づく省面積・省エネルギー脳型LSI実現

鬼沢直哉, 松宮一道, 羽生貴弘

IEICEソサイエティ大会, Sep 12, 2017
視覚的注意計算モデルのハードウェア実装に向けた基礎的考察

西野海斗, 鬼沢直哉, 松宮一道, 塩入諭, 羽生貴弘

平成29年度電気関係学会東北支部連合大会, Aug 24, 2017
脳型計算に基づく車載ネットワークの不正侵入検出法

須田拓樹, 夏井雅典, 羽生貴弘

平成29年度電気関係学会東北支部連合大会, Aug 24, 2017
ストカスティック演算に基づく省エネルギー脳型LSI実現の展望

鬼沢直哉, 松宮一道, 羽生貴弘

第30回回路とシステムのワークショップ, May 11, 2017
ストカスティック演算に基づくFIRフィルタの振幅特性測定

鎌田裕成, 越田俊介, 鬼沢直哉, 阿部正英, 羽生貴弘, 川又政征

第30回回路とシステムのワークショップ, May 11, 2017
Technologies to automatically design environments for low energy consumption and highly functional VLSI processors based on non-volatile memory

Takahiro Hanyu

3rd CIES Technology Forum, Mar 22, 2017
不揮発FPGAを用いた脳型情報処理アクセラレータ

鈴木大輔, 羽生貴弘

2017電子情報通信学会総合大会, Mar 22, 2017
ストカスティック演算に基づくディジタルフィルタにおける周波数振幅特性の測定法に関する一検討

鎌田裕成, 越田俊介, 鬼沢直哉, 阿部正英, 羽生貴弘, 川又政征

電気学会制御研究会, Mar 13, 2017
Challenge of a Nonvolatile FPGA for a Brainware LSI Platform

Daisuke Suzuki, Takahiro Hanyu

The 4th International Symposium on Brainware LSI, Feb 22, 2017
Brain-Inspired Computing for Error-Resilient VLSI System

Masanori Natsui, Takahiro Hanyu

The 4th International Symposium on Brainware LSI, Feb 22, 2017
Stochastic Computation for Deep Neural Networks

Naoya Onizawa, Takahiro Hanyu

The 4th International Symposium on Brainware LSI, Feb 22, 2017
不揮発マイコン向け高速・低電力アナログ/ディジタル変換器の構成

玉越晃, 夏井雅典, 羽生貴弘

デザインガイア2016, Nov 28, 2016
ストカスティック演算に基づく省エネルギーガンマトーンフィルタのハードウェア実現

鬼沢直哉, 越田俊介, 坂本修一, 阿部正英, 川又政征, 羽生貴弘

第３１回信号処理シンポジウム, Nov 8, 2016

Professional Memberships

Mar, 2009 - Present

The Japan Society of Applied Physics
Aug, 1986 - Present

Information Processing Society of Japan
Aug, 1984 - Present

The Institute of Electronics, Information and Communication Engineers
米国電気電子工学会(The Institute of Electrical and Electronics Engineers)

Research Projects

Device-Model-Based Electronics

Grant-in-Aid for Scientific Research, Jan, 1986 - Present
Nonvolatile Logic-in-Memory VLSI Technology

Grant-in-Aid for Scientific Research, Jan, 1986 - Present
Multiple-Valued Integrated Systems

Grant-in-Aid for Scientific Research, Oct, 1983 - Present
Development of a high-speed and ultra-low-power die-hard logic LSI fundamental technology for IoT applications

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (A), Japan Society for the Promotion of Science, Apr, 2021 - Mar, 2025
確率的デバイスモデルに基づく量子モンテカルロ計算ハードウェアプラットフォーム構築

科学研究費助成事業, 基盤研究(B), 日本学術振興会, Apr, 2021 - Mar, 2025

鬼沢直哉, 羽生貴弘
スピントロニクスベース高性能・省電力・高信頼IoTセンサノードの基盤研究開発

科学研究費助成事業, 基盤研究(B), 日本学術振興会, Apr, 2021 - Mar, 2025

夏井雅典, 羽生貴弘
脳型コンピューティング向けダーク・シリコンロジックLSIの基盤技術開発

科学研究費助成事業, 基盤研究(S), 日本学術振興会, May, 2016 - Mar, 2021

羽生貴弘, 夏井雅典, 米田友洋, 今井雅, 池田正二, 鬼沢直哉, 村口正和
Study on Implementation for Greatly Reducing Power Dissipation of Serial Communication Mechanisms

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (A), Japan Society for the Promotion of Science, Apr, 2015 - Mar, 2018

YONEDA Tomohiro
脳型コンピューティング向けダーク・シリコンロジックLSIの基盤技術開発

科学研究費助成事業, 基盤研究(A), 日本学術振興会, Apr, 2016 - Mar, 2017

羽生貴弘, 米田友洋, 今井雅, 鬼沢直哉
Nonvolatile-device-based PVT-variation-resilient VLSI system

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, Apr, 2010 - Mar, 2014

HANYU TAKAHIRO, NATSUI Masanori
Implementation of a High-Speed LDPC Decoder LSI Based on a Multiple-Valued Full-Duplex Data-Transfer Technique

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, 2006 - 2008

HANYU Takahiro, MOCHIZUKI Akira, MATSUMOTO Atsushi, NATSUI Masanori
不揮発性デバイスに基づくクイックオンVLSIシステムの構成

科学研究費助成事業, 萌芽研究, 日本学術振興会, 2006 - 2007

羽生貴弘, 松本敦, 望月明
Implementation of a High-Speed Asynchronous Data Transfer VLSI Based on Bidirectional Current-Mode Multiple-Valued Circuit Techniques

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (C), Japan Society for the Promotion of Science, 2003 - 2005

HANYU Takahiro, MOCHIZUKI Akira
Implementation of a Transfer-Bottleneck-Free Multiple-Valued Logic-in-Memory VLSI and Its Application

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, 2001 - 2004

HANYU Takahiro, KAMEYAMA Michitaka, MOCHIZUKI Akira, KIMURA Hiromitsu
多値技術に基づく高速データ転送とそのマルチメディアVLSIプロセッサへの応用

科学研究費助成事業, 基盤研究(C), 日本学術振興会, 2002 - 2002

羽生貴弘, 米田友洋, 川人祥二, 亀山充隆
Implementation of a High-Performance Multiple-Valued Current-Mode VLSI System with Low-Power and Highly Reliable Capabilities

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (C), Japan Society for the Promotion of Science, 2000 - 2002

HANYU Takahiro
Interconnection-Bottleneck-Free VLSI System Based on Dual-Rail Multiple-Valued Digital Computing

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, 2000 - 2002

KAMEYAMA MICHITAKA, HANYU TAKAHIRO
Implementation of a One-Transistor Multiple-Valued Content-Addressalbe Memory and Its Application

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B)., Japan Society for the Promotion of Science, 1997 - 2000

HANYU Takahiro, KAMEYAMA Michitaka
高速・低電力電流モード多値算術演算VLSI回路の試作

科学研究費助成事業, 奨励研究(A), 日本学術振興会, 1998 - 1999

羽生貴弘
Development of a Chip Family for Ultra-Highly-Parallel Multiple-Valued Integrated Circuits and Its Applications

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, 1997 - 1999

KAMEYAMA Michitaka, HARIYAMA Masanori, HANYU Takahiro

Industrial Property Rights

特開2006-246394 完全二重非同期通信システム

羽生貴弘, 高橋知宏
特開2005-235307 磁気抵抗効果素子を用いたロジックインメモリ回路

羽生貴弘, 木村啓明
特開2004-264896 論理演算回路，論理演算装置および論理演算方法

亀山充隆, 羽生貴弘, 木村啓明, 藤森敬和, 中村孝, 高須秀視
W02003/065583 論理演算回路および論理演算方法

亀山充隆, 羽生貴弘, 木村啓明, 藤森敬和, 中村孝, 高須秀視
W02003/065582 論理演算回路および論理演算方法

亀山充隆, 羽生貴弘, 木村啓明, 藤森敬和, 中村孝, 高須秀視
5,930,161 Nonvolatile Content Addressable Memory
5,808,929 Nonvolatile Content Addressable Memory

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スピントロニクス技術を用いた不揮発性集積回路の試作に成功－磁石と半導体を組み合わせて待機電力をゼロにする新しい集積回路－

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Aug 21, 2008

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高機能・超低消費電力スピンデバイス・ストレージ基盤技術の開発

Dec, 2007 - Dec, 2007

スピンを操る技術をもとに，産学連携で研究開発を推進し，メモリ・ロジック回路，ストレージ等の高機能・超低消費電力コンピューティングのための基盤技術を開発する
多値2値融合・非同期データ転送に基づく高速・低電力LDPCデコーダLSIの開発

Jul, 2007 - Jul, 2007

多値2値融合・非同期データ転送に基づく高速・低電力LDPCデコーダLSIの開発
TMRロジックに基づく動的再構成可能回路技術に関する研究

Apr, 2004 - Apr, 2004

TMRロジックに基づく動的再構成可能回路技術に関する研究
不揮発性ロジックに基づく瞬時再構成可能VLSIの開発

Apr, 2004 - Apr, 2004

不揮発性ロジックに基づく瞬時再構成可能VLSIの開発

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