 | | |
| |
| | SASAO Tsutomu Last updated: Sep 22, 2019 at 10:21 | Name | SASAO Tsutomu |
|---|
Affiliation | Meiji University |
|---|
Section | School of Science and Technology |
|---|
Job title | Professor |
|---|
Degree | Ph.D(Osaka University) |
|---|
|
Published Papers Shinobu Nagayama,Tsutomu Sasao,Jon T. Butler 48th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2018, Linz, Austria, May 16-18, 2018 144-149 2018 [Refereed] Jon T. Butler,Tsutomu Sasao 48th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2018, Linz, Austria, May 16-18, 2018 138-143 2018 [Refereed] Tsutomu Sasao 48th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2018, Linz, Austria, May 16-18, 2018 50-55 2018 [Refereed] Hiroki Nakahara,Tsutomu Sasao IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy 1-5 2018 [Refereed] Array,Tsutomu Sasao,Xiaoqing Wen IEEE Trans. on CAD of Integrated Circuits and Systems 37(6) 1185-1196 2018 [Refereed] Misc International Symposium on Multiple-valued Logic (ISMVL-2008) 57-63 May 2008 S. Nagayama International Symposium on Multiple-valued Logic (ISMVL-2008) May 2008 On the number of variables to represent sparse logic functions 17th International Workshop on Logic & Synthesis (IWLS-2008) 233-239 Jun 2008 H. Nakahara, M. Matsuura, Y. Kawamura, and J.T. Butler, 39th International Symposium on Multiple-Valued Logic (ISMVL 2009) 362-369 May 2009 S. Nagayama他1名 39th International Symposium on Multiple-Valued Logic (ISMVL 2009)(IEEE,USA) 349-355 May 2009 Books etc Progress in Applications of Boolean Functions Jon T. Butler (Part:Supervisor) Morgan & Claypool Publishers (USA) Jan 2010 |
Memory-Based Logic Synthesis Springer(USA) Mar 2011 |
Applications of Zero-Suppressed Decision Diagrams Jon T. Butler (Part:Supervisor) Dec 2014 |
Conference Activities & Talks Numerical function generators using decision diagrams for discrete functions Proceedings of the 18th International Workshop on Post-Binary ULSI Systems 20 May 2009 S. Nagayama, J. T. Butler Index generation functions: Recent developments IEEE International Symposium on Multiple-valued Logic May 2011 Tuusula, Finland (基調講演) Linear transformations for variable reduction Reed Muller 2011 Workshop 25 May 2011 Linear decomposition of logic functions: Theory and applications The 20th International Workshop on Logic and Synthesis (IWLS-2011) 3 Jun 2011 A fast head-tail expression generator for TCAM: Application to packet classification IEEE Computer Society Annual Symposium on VLSI (ISVLSI-2012) 19 Aug 2012 IEEE Computer Society I. Syfalni Research Grants & Projects High-speed pattern matching Project Year: Apr 2014 - Mar 2018 |
|
|
|
| |
