論文

査読有り
1993年7月

A SWITCHED-CAPACITOR CAPACITANCE MEASUREMENT CIRCUIT WITH THE VERNIER SCALE

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
  • K KONDO
  • ,
  • K WATANABE

E76A
7
開始ページ
1139
終了ページ
1142
記述言語
英語
掲載種別
研究論文(学術雑誌)
出版者・発行元
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

To improve measurement accuracy and speed, a switched-capacitor capacitance measurement circuit with the vernier scale is developed. Its process consists of a coarse measurement by charge-balancing A-D conversion and a fine measurement by single-slope A-D conversion. A prototype using discrete components confirms the principles of operation.

リンク情報
Web of Science
https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:A1993LP50100014&DestApp=WOS_CPL
URL
https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=0027629126&origin=inward
ID情報
  • ISSN : 0916-8508
  • eISSN : 1745-1337
  • SCOPUS ID : 0027629126
  • Web of Science ID : WOS:A1993LP50100014

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