This report discusses impedance determination of a linear equivalent circuit (LEC) in an EMC macro model, LECCS I/O. The 2-port LECCS I/O model the authors had proposed based on 2-port measurement by a vector network analyzer (VNA) was found to be affected by an external circuit connected to the input terminals of CMOS gates. To remove the defect, this report investigated a 3-port LECCS I/O model with 3-port VNA. The 3-port model includes the input circuit of CMOS gates and the three ports of the model mean the power-supply terminal, the output terminal, and the input terminal to the ground terminal. The proposed 3-port model with 3-port VNA was used for power-ground impedance simulation by changing the impedances of external input and output circuits. As a result, the impedance simulation was in good agreement with measurements in higher frequency range compared with the previous 2-port model with 2-port VNA.