論文

査読有り
2015年9月10日

Security simulation against side-channel attacks on Advanced Encryption Standard circuits based on equivalent circuit model

IEEE International Symposium on Electromagnetic Compatibility
  • Kengo Iokibe
  • ,
  • Kazuhiro Maeshima
  • ,
  • Tetsushi Watanabe
  • ,
  • Yoshitaka Toyota

2015-
開始ページ
224
終了ページ
229
記述言語
英語
掲載種別
研究論文(国際会議プロシーディングス)
DOI
10.1109/ISEMC.2015.7256163
出版者・発行元
Institute of Electrical and Electronics Engineers Inc.

An equivalent circuit model was applied to a cryptographic module to simulate the resistance of the module against side-channel attacks. The cryptographic module involved two fiel programmable gate arrays (FPGAs), on which an Advanced Encryption Standard (AES) circuit was implemented on one of them. The equivalent circuit model proposed in the previous literature was improved in terms of the accuracy of model parameters. Resistance against side-channel attacks was simulated in a more practical configuratio with the improved model than that in the previous work. Resistance was simulated with random plaintexts (input values) to the cryptographic circuit, whereas a biased plaintext set was used to simplify simulation. The simulation was carried out with two decoupling configuration for the power distribution network of the FPGA core that the AES circuit was implemented in. The results obtained from simulation confirme that the equivalent circuit model allowed side-channel resistance to be precisely predicted.

リンク情報
DOI
https://doi.org/10.1109/ISEMC.2015.7256163
ID情報
  • DOI : 10.1109/ISEMC.2015.7256163
  • ISSN : 2158-1118
  • ISSN : 1077-4076
  • SCOPUS ID : 84953847634

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