Sato Toshinori

J-GLOBAL         Last updated: Jan 9, 2020 at 19:03
Sato Toshinori
Fukuoka University
Faculty of Engineering, Department of Electronics Engineering and Computer Science
Research funding number

Research Areas


Academic & Professional Experience

Jan 2006
Mar 2008
Oct 1999
Dec 2005
Apr 1991
Sep 1999


Apr 1989
Mar 1991
電子工学専攻, Graduate School, Division of Engineering, Kyoto University

Awards & Honors

Apr 2008
第10回LSI IPデザイン・アワード・MeP賞, LSI IPデザイン・アワード運営委員会
Oct 2007
Excellent Paper Awards, International Conferenceon Computer and Information Technology
Indirect Tag Search Mechanism for Instruction Window Energy Reduction
May 2007
最優秀論文賞, 先進的計算基盤システムシンポジウム
Jul 2003
平成15年度山下記念研究賞, 情報処理学会
May 2000
平成11年度論文賞, 情報処理学会

Published Papers

Trading Accuracy for Power with a Configurable Approximate Adder
Toshinori Sato, Tongxin Yang, Tomoaki Ukezono
IEICE Transactions on Electronics   E102-C(4) 260-268   Apr 2019   [Refereed]
Design and Analysis of Approximate Multipliers with a Tree Compressor
Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E102-A(3) 532-543   Mar 2019   [Refereed]
Design and Analysis of A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier
Tongxin Yang, Tomoaki Ukezono, Toshinori Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E101-A(12)    Dec 2018   [Refereed]
Optimizing Power Heterogeneous Functional Units for Dynamic and Static Power Reduction
Toshinori Sato, Yoshimi Shibata
Electronics   3(4) 661-674   Dec 2014   [Refereed]
佐藤寿倫, 矢野憲, 安浦寛人
日本信頼性学会誌「信頼性」   35(8) 452   Dec 2013
A Selective Replacement Method for Timing-Error-Predicting Flip-Flops
Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida
Journal of Circuits, Systems and Computers   21(6)    Nov 2012
Short Term Cell-flipping Technique for Mitigating SNM Degradation Due to NBTI
Yuji Kunitake, Hiroto Yasuura
IEICE Transactions on Electronics   E94-C(4) 520-529   Apr 2011
Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment
Yuji Kunitake, Kazuhiro Mima, Toshinori Sato, Hiroto Yasuura
IEICE Transactions on Electronics   E92-C(4) 483-491   Apr 2009   [Refereed]
A Simple Mechanism for Collapsing Instructions under Timing Speculation
Toshinori Sato
IEICE Transactions on Electronics   E91-C(9) 1394-1401   Sep 2008   [Refereed]
Cascading ALU Operations for Improving Timing Yield
Shingo Watanabe, Masanori Hashimoto, Toshinori Sato
IPSJ Transactions on Advanced Computing Systems   1(2) 12-21   Aug 2008   [Refereed]
佐藤寿倫, 舟木敏正
情報処理学会論文誌   49(6) 2005-2015   Jun 2008   [Refereed]
佐藤寿倫, 国武勇次
情報処理学会論文誌   49(6) 2029-2042   Jun 2008   [Refereed]
A Low-Power Instruction Issue Queue for Microprocessors
Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato
IEICE Transactions on Electronics   E91-C(4) 400-409   Apr 2008   [Refereed]
Folding Active List for High Performance and Low Power
Yuichiro Imaizumi, Toshinori Sato
High-Performance Computing   4759 33-42   Jan 2008   [Refereed]
Realizing Energy-Efficient MultiCore Processors by Utilizing Speculative Thread-Level Parallelism
Toshinori Sato, Yuu Tanaka, Hidenori Sato, Toshimasa Funaki, Takenori Koshiro, Akihiro Chiyonobu
International Journal of Computers and their Applications   14(2) 79-91   Jun 2007   [Refereed]
Low Power Cache Memories Prioritizing Data
Akihiro Chiyonobu, Seiichiro Fujii, Toshinori Sato
IPSJ Transactions on Advanced Computing Systems   48(SIG8(ACS18)) 114-126   May 2007   [Refereed]
An Energy-Efficient Instruction Scheduling Technique Exploiting Cache Miss Information
Akihiro Chiyonobu, Toshinori Sato
IEICE Transactions   J89-D(12) 2590-2601   Dec 2006   [Refereed]
A Fast Fault Detection Circuit for Low-power Adders with Timing Error Tolerance
Mikio Yamahara, Kazuhiro Mima, Akihiro Chiyonobu, Toshinori Sato
IPSJ Transactions on Advanced Computing Systems   47(SIG18(ACS16)) 65-79   Nov 2006   [Refereed]
A Leakage-Energy-Reduction Technique for Cache Memories in Embedded Processors
Seiichiro Fujii, Akihito Sakanaka, Akihiro Chiyonobu, Toshinori Sato
Journal of Embedded Computing   2(1) 49-55   Oct 2006   [Refereed]
Energy-Efficient Instruction Scheduling Utilizing Cache Miss Information
Akihiro Chiyonobu and Toshinori Sato
ACM SIGARCH Computer Architecture News   34(1) 65-70   Mar 2006
情報処理学会学会誌   46(11) 1212-1217   Nov 2005
An Energy-Efficient Clustered Superscalar Processor
Toshinori Sato, Akihiro Chiyonobu
IEICE Transactions on Electronics   E88-C(4) 544-551   Apr 2005   [Refereed]
Exploiting Sub-word Parallelism for Dependable Processors
Toshinori Sato
WSEAS Transactions on Information Science and Applications   6(1) 1051-1056   Nov 2004   [Refereed]
田中康一郎, 林悠平, 澤田直, 佐藤寿倫, 有田五次郎
電子情報通信学会論文誌 D1   J87-D1(6) 640-640   Jun 2004   [Refereed]
A Leakage-Energy-Reduction Technique for Highly-Associative Caches in Embedded Systems
Akihito Sakanaka, Seiichirou Fujii, Toshinori Sato
ACM SIGARCH Computer Architecture News   32(3) 50-54   Jun 2004
神代剛典, 佐藤寿倫
情報処理学会論文誌コンピューティングシステム   45(SIG 1(ACS 4)) 43-53   Jan 2004   [Refereed]
A Transparent Transient Faults Tolerance Mechanism for Superscalar Processors
Toshinori Sato
IEICE Transactions on Information and Systems   E86-D(12) 2508-2516   Dec 2003
Combining Variable Latency Pipeline with Instruction Reuse for Execution Latency Reduction
Toshinori Sato, Itsujiro Arita
Systems and Computers in Japan   34(12) 11-21   Nov 2003
Constructive Timing Violation for Improving Energy Efficiency
Toshinori Sato, Itsujiro Arita
Compilers and Operating Systems for Low Power      Sep 2003   [Refereed]
千代延昭宏, 佐藤寿倫, 有田五次郎
電子情報通信学会論文誌 C   J86-C(8) 826-835   Aug 2003   [Refereed]
A Trace-Level Value Predictor for Contrail Processors
Takenori Koushiro, Toshinori Sato, Itujiro Arita
ACM SIGARCH Computer Architecture News   31(3) 42-47   Jun 2003
佐藤寿倫, 有田五次郎
電子情報通信学会論文誌 D-I   J85-D-I(12) 1103-1113   Dec 2002   [Refereed]
Evaluating Influence of Compiler Optimizations on Data Speculation
Toshinori Sato, Kiichi Sugitani, Akihiko Hamano, Itsujiro Arita
Journal of Information Science and Engineering,   18(6) 1027-1036   Nov 2002   [Refereed]
Potential of Constructive Timing-Violation
Toshinori Sato, Itsujiro Arita
EICE Transactions on Electronics   E85-C(2) 323-330   Feb 2002   [Refereed]
Evaluating the Impact of Reissued Instructions on Data Speculative Processor Performance
Toshinori Sato
Microprocessors and Microsystems   25(9-10) 469-482   Jan 2002   [Refereed]
The KIT COSMOS Processor: A Low-Complexity Superscalar Processor
Toshinori Sato, Toshiyuki Yamamoto, Itsujiro Arita
International Journal of Computer & Information Science   2(4) 182-190   Dec 2001   [Refereed]
Quantitative Evaluation of Pipelining and Decoupling a Dynamic Instruction Scheduling Mechanism
Toshinori Sato
Journal of Systems Architecture   46(13) 1231-1252   Nov 2000   [Refereed]
Evaluating Trace Cache on Moderate Scale Processors
Toshinori Sato
IEE Proceedings on Computers and Digital Techniques   147(6) 369-374   Nov 2000   [Refereed]
2.44 GFLOPS 300MHz Floating-Point Vector Processing Unit for High Performance 3D Graphics Computing
Nobuhiro Ide, Masashi Hirano, Yukio Endo, Shin'ichi Yoshioka, Hiroaki Murakami, Atsushi Kunimatsu, Toshinori Sato, Takayuki Kamei, Toyoshi Okada, Masakazu Suzuoki
IEEE Journal of Solid-State Circuits   35(7) 1025-1033   Jul 2000   [Refereed]
Vector Units Architecture for Emotion Synthesis
Atsushi Kunimatsu, Nobuhiro Ide, Toshinori Sato, Yukio Endo, Hiroaki Murakami, Takayuki Kamei, Masashi Hirano, Fujio Ishihara, Haruyuki Tago, Masaaki Oka, Akio Ohba, Teiji Yutaka, Toyoshi Okada, Masakazu Suzuoki
IEEE Micro   20(2) 40-47   Mar 2000   [Refereed]
A Simulation Study of Combining Load Value and Address Predictors
Toshinori Sato
International Journal of High Speed Computing   10(3) 301-325   Sep 1999   [Refereed]
2109-2118   40(5)    May 1999   [Refereed]
情報処理学会論文誌   40(5) 2093-2108   May 1999   [Refereed]
A Microprocessor Architecture Utilizing Histories of Dynamic Sequences Saved in Distributed Memories
Toshinori Sato
IEICE Transactions on Electronics   E81-C(9) 1398-1407   Sep 1998   [Refereed]
Resolving Load Data Dependency using Tunneling-Load Technique
Toshinori Sato
IEICE Transactions on Information and Systems   E81-D(8) 829-838   Aug 1998   [Refereed]
電子情報通信学会論文誌 D-I,   J81-D-I(6) 728-737   Jun 1998   [Refereed]
Hiding Data Cache Latency with Load Address Prediction
Toshinori Sato, Hiroshige Fujii, Seigo Suzuki
IEICE Transactions on Information and Systems   E79-D(11) 1523-1532   Nov 1996   [Refereed]
永松正人, 佐藤寿倫, 田胡治之
東芝レビュー   50(12) 883-886   Dec 1995
Performance Evaluation of a Processing Element for an On-Chip Multiprocessor
Masafumi Takahashi, Hiroshige Fujii, Emi Kaneko, Takeshi Yoshida, Toshinori Sato, Hiroyuki Takano, Haruyuki Tago, Seigo Suzuki, Nobuyuki Goto
EICE Transactions on Electronics   E77-C(7) 1092-1100   Jul 1994   [Refereed]
320 MFLOPS CMOS Floating-point Processing Unit for Superscalar Processors
Nobuhiro Ide, Hiroto Fukuhisa, Hiroyuki Takano, Takeshi Yoshida, Toshinori Sato, Haruyuki Tago
IEEE Denshi Tokyo   32 104-109   1993   [Refereed]
奥田亮輔, 佐藤寿倫, 小野寺秀俊, 田丸啓吉
電子情報通信学会論文誌 A   J73-A(3) 536-543   Mar 1990   [Refereed]


佐藤 寿倫、請園 智玲
福岡大学工学集報   (102) 43-49   Mar 2019
Typical Case Oriented Design Approach by Timing Error Prediction to Tolerate Process Variability
Ken Yano, Toshinori Sato
Fukuoka University Review of Technological Sciences   95 7-16   Sep 2015
佐藤 寿倫、高橋 伸弥
福岡大学研究部論集 F:推奨研究編   2 19-24   Mar 2015
福岡大学研究推進部 Research   13(3) 3-4   Sep 2008

Books etc

佐藤 寿倫,請園 智玲,他60名 (Part:Joint Work)
技術情報協会   Jan 2019   
VLSI Design and Test for Systems Dependability
Shojiro Asai (editor)
Springer   Jul 2018   ISBN:978-4-431-56592-5
コンピュータアーキテクチャ 定量的アプローチ 第5版
中條拓伯, 天野英晴, 鈴木貢, 吉瀬謙二, 佐藤寿倫 (Part:Joint Translation)
翔泳社   Mar 2014   ISBN:978-4798126234
知識ベース, 6群5編2章 スレッドレベル並列コンピュータ
佐藤寿倫, 小林良太郎, 中條拓伯, 大津金光 (Part:Joint Work)
電子情報通信学会   May 2010   
知識ベース, 6群5編4章 ベクトルコンピュータ
佐藤寿倫, 平澤将一, 林宏雄 (Part:Joint Work)
電子情報通信学会   May 2010   

Conference Activities & Talks

Evaluation on Configurable Approximate Circuit for Aging-Induced Timing Violation Tolerance
Sato Toshinori, Tomoaki Ukezono
24th IEEE Pacific Rim International Symposium on Dependable Computing   Dec 2019   
Correcting Sign Calculation Errors in Configurable Approximations
Sato Toshinori, Tomoaki Ukezono
15th IEEE Asia Pacific Conference on Circuits and Systems   Nov 2019   
On Applications of Configurable Approximation to Irregular Voltage
Sato Toshinori, Tomoaki Ukezono
5th IEEE Nordic Circuits and Systems Conference   Oct 2019   
Tolerating Aging-Induced Timing Violations via Configurable Approximations
Sato Toshinori, Tomoaki Ukezono
8th IEEE Global Conference on Consumer Electronics   18 Oct 2019   
An Approximate Multiply-Accumulate Unit with Low Power and Reduced Area
Tongxin Yang, Toshinori Sato, Tomoaki Ukezono
IEEE Computer Society Annual Symposium on VLSI   Jul 2019   IEEE CS

Research Grants & Projects

Project Year: 2017   
Project Year: 2014 - 2017
Project Year: 2011 - 2014
Project Year: 2008 - 2010
Project Year: 2008 - 2009


USP 6,643,767 : Instruction scheduling system of a processor
USP 6,516,409 : Processor provided with a data value prediction circuit and a branch prediction circuit
USP 6,415,380 : Speculative execution of a load instruction by associating the load instruction with a previously executed store instruction
USP 6,119,220 : Method of and apparatus for supplying multiple instruction strings whose addresses are discontinued by branch instructions
USP 5,903,768 : Pipelined Microprocessor and load address prediction method therefor