Shuhei Iwade

Profile Information

Affiliation: Professor, Faculty of Information Science and Technology, Department of Computer Science, Osaka Institute of Technology

Degree: 理学博士(大阪大学)

J-GLOBAL ID: 200901076580621818
researchmap Member ID: 5000063400

External link: http://www.is.oit.ac.jp/~iwade

Research Interests

Research Areas

Manufacturing technology (mechanical, electrical/electronic, chemical engineering) / Electronic devices and equipment /

Research History

1998 - 2003

三菱電機(株)システムLSI事業化推進センター先端システムLSI技術開発部長
1997 - 2003

Department Manager of System LSI Design R&D
1997 - 1998

三菱電機(株)ULSI研究所システムLSIコア開発部長
Development

Education

- 1978

Osaka University
- 1976

School of Science, Osaka University

Misc.

Test structure measuring inter- and intralayer coupling capacitance of interconnection with subfemtofarad resolution

T Kunikiyo, T Watanabe, T Kanamoto, H Asazato, M Shirota, K Eikyu, Y Ajioka, H Makino, K Ishikawa, S Iwade …

IEEE TRANSACTIONS ON ELECTRON DEVICES, 51(5) 726-735, May, 2004
A wide range 1.0-3.6 V 200 Mbps, push-pull output buffer using parasitic bipolar transistors

T Shimada, H Notani, Y Nakase, H Makino, S Iwade

IEICE TRANSACTIONS ON ELECTRONICS, E87C(4) 571-577, Apr, 2004
Selective-sets resizable cache memory design for high-performance and low-power CPU core

T Kurafuji, Y Nakase, H Takata, Y Imamura, R Akiyama, T Yamanaka, A Iwabu, S Yasuda, T Miwa, Y Nunomura …

IEICE TRANSACTIONS ON ELECTRONICS, E87C(4) 535-542, Apr, 2004
A low-power microcontroller with body-tied SOI technology

H Sato, Y Nunomura, N Itoh, K Nii, K Yoshida, H Ito, J Nakanishi, H Takata, Y Nakase, H Makino …

IEICE TRANSACTIONS ON ELECTRONICS, E87C(4) 563-570, Apr, 2004
A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications

K Nii, Y Tsukamoto, T Yoshizawa, S Imaoka, Y Yamagami, T Suzuki, A Shibayama, H Makino, S Iwade

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 39(4) 684-693, Apr, 2004
A low standby current DSP core using improved ABC-MT-CMOS with charge pump circuit

H Notani, M Koyama, R Mano, H Makino, Y Matsuda, O Tomisawa, S Iwade

IEICE TRANSACTIONS ON ELECTRONICS, E86C(4) 597-603, Apr, 2003
Signal integrity design and analysis for a 400 MHz RISC microcontroller

A Yamada, Y Nunomura, H Suzuki, H Sato, N Itoh, T Kagemoto, H Ito, T Kurafuji, N Yoshioka, J Nakanishi …

IEICE TRANSACTIONS ON ELECTRONICS, E86C(4) 635-642, Apr, 2003
Signal integrity design and analysis for a 400 MHz RISC microcontroller

A Yamada, Y Nunomura, H Suzuki, H Sato, N Itoh, T Kagemoto, H Ito, T Kurafuji, N Yoshioka, J Nakanishi …

IEICE TRANSACTIONS ON ELECTRONICS, E86C(4) 635-642, Apr, 2003
Realistic scaling scenario for sub-100 nm embedded SRAM based on 3-dimensional interconnect simulation

Y Tsukamoto, T Kunikiyo, K Nii, H Makino, S Iwade, K Ishikawa, Y Inoue, N Kotani

IEICE TRANSACTIONS ON ELECTRONICS, E86C(3) 439-446, Mar, 2003
Realistic scaling scenario for sub-100 nm embedded SRAM based on 3-dimensional interconnect simulation

Y Tsukamoto, T Kunikiyo, K Nii, H Makino, S Iwade, K Ishikawa, Y Inoue, N Kotani

IEICE TRANSACTIONS ON ELECTRONICS, E86C(3) 439-446, Mar, 2003
Multimedia Accelerator ACE:A Practical approach for Multimedia Applications

C. Nakanishi, I. Minematsu, H. Sato, K. Nakakimura, T. Arakawa, S. Iwade

IPSJ Transactions on High Performance Computing Systems, 43(SIG6(HPS 5)) 230-243, 2002
Physical Desingn Methodology for On-chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor

H. Takata, R. Akiyama, T. Yamanaka, H. Ohkuma, Y. Suetsugu, T. Kanaoka, S. Kumaki, K. Ishihara, A. Hanami, T. Matsumura …

IEICE Transaction on Electronics, E85-C(2), 2002
A Clock Distribution Circuit Layout Design Tool for Large-scale and High-speed ASICs

TERAI Masayuki, KANAMOTO Toshiki, KOTANI Ken, SHIBAYAMA Yasunori, OKAZAKI Kaoru, HORIBA Yasutaka, IWADE Shuhei

Transactions of Information Processing Society of Japan, 43(5) 1294-1303, 2002
'Multimedia Accelerator ACE:A Practical approach for Multimedia Applications'

IPSJ Transactions on High Performance Computing Systems, 43(SIG6(HPS 5)) 230-243, 2002
'Physical Desingn Methodology for On-chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor'

IEICE Transaction on Electronics, E85-C(2), 2002
The D30V/MPEG multimedia processor

H Takata, T Watanabe, T Nakajima, T Takagaki, H Sato, A Mohri, A Yamada, T Kanamoto, Y Matsuda, S Iwade …

IEEE MICRO, 19(4) 38-47, Jul, 1999
The D30V/MPEG multimedia processor

H Takata, T Watanabe, T Nakajima, T Takagaki, H Sato, A Mohri, A Yamada, T Kanamoto, Y Matsuda, S Iwade …

IEEE MICRO, 19(4) 38-47, Jul, 1999
基盤バイアス自動制御MT-COS回路技術を用いたLSI低消費電力化

荒川隆彦, 牧野博之, 辻橋良樹, 新居浩二, 森嶋哉圭, 早川康, 清水徹, 岩出秀平, 小山健

電子情報通信学会論文誌,C-Ⅱ, J82-C-Ⅱ(9) 505-512, 1999
Novel Memory Cell for Multiport RAM on 0.5μm CMOS Sea-of-Gate

K. Nii, H. Maeno, T. Osawa, S. Iwade, S. Kayano, H. Shibata

IEEE Jourmal of Solid-State Circuits, 30(3) 316-320, 1995
'Novel Memory Cell for Multiport RAM on 0.5μm CMOS Sea-of-Gate'

IEEE Jourmal of Solid-State Circuits, 30(3) 316-320, 1995

Books and Other Publications

実用プロセッサ技術

ムイスリ出版, Apr, 2009 (ISBN: 9784896411614)
明快解説・箇条書式ディジタル回路

ムイスリ出版, Apr, 2006 (ISBN: 9784896411270)

Profile Information

Research Interests

Research Areas

Research History

Education

Misc.

Books and Other Publications

Professional Memberships

Research Projects

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