2017年11月3日
Optimization of the balance between the gate-Drain capacitance and the common source inductance for preventing the oscillatory false triggering of fast switching GaN- FETs
2017 IEEE Energy Conversion Congress and Exposition, ECCE 2017
- ,
- ,
- 巻
- 2017-January
- 号
- 開始ページ
- 405
- 終了ページ
- 412
- 記述言語
- 英語
- 掲載種別
- 研究論文(国際会議プロシーディングス)
- DOI
- 10.1109/ECCE.2017.8095811
- 出版者・発行元
- IEEE
© 2017 IEEE. GaN- FETs are attractive switching devices for their fast switching capability. However, they often suffer from the oscillatory false triggering, i.e. a series of self-sustaining repetitive false triggering induced after a fast switching. The purpose of this paper is to derive a design instruction to prevent this phenomenon. According to the previous study, the oscillatory false triggering was found to be caused by a parasitic oscillator circuit formed of a GaN- FET, its parasitic capacitance, and the parasitic inductance of the wiring. This paper analyzed the oscillatory condition to elucidate the design requirement to prevent the oscillatory false triggering. As a result, balancing the gate-drain parasitic capacitance and the common source inductance to achieve an appropriate ratio was found to be essential for preventing the oscillatory false triggering. Experiment successfully supported prevention of this phenomenon by balancing these two factors.
- リンク情報
-
- DOI
- https://doi.org/10.1109/ECCE.2017.8095811
- Web of Science
- https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:000426847400058&DestApp=WOS_CPL
- Scopus
- https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85041460362&origin=inward
- Scopus Citedby
- https://www.scopus.com/inward/citedby.uri?partnerID=HzOxMe3b&scp=85041460362&origin=inward
- ID情報
-
- DOI : 10.1109/ECCE.2017.8095811
- ISSN : 2329-3721
- SCOPUS ID : 85041460362
- Web of Science ID : WOS:000426847400058