齋藤 寛

H. Saito, H. Nakamura, M. Fujita, and T. Nanya : Logic Optimization of Asynchronous Speed-Independent Circuits Using Transduction Methods 

IPSJ Journal 4(5) 1289-1299 2004年  

E. Kim, H. Saito, J-G. Lee, D-I. Lee, H. Nakamura, and T. Nanya. : "Performance optimization of Synchronous Control Units for Datapaths with Variable Delay Arithmetic Units" 

In Proc. Asia South Pacific Design Automation Conference, Kitakyusyu, Japan pp.816-819 2003年  

H. Saito, H. Nakamura, M. Fujita, and T. Nanya. : "Logic Optimization of Asynchronous SI Controllers using Transduction Method" 

In. Proc. Asia South Pacific Design Automation Conference, Kitakyusyu, Japan pp.197-202 2003年  

E. Kim, H. Saito, J-G. Lee, D-I. Lee, H. Nakamura, and T. Nanya. : "Distributed Synchronous Control Units for Data flow Graphs under Allocation of Telescopic Arithmetic Units" 

In Proc. Design Automation and Test in Europe, Munich, Germany pp.276-281 2003年  

H. Saito, E. Kim, N. Sretaseereekul, M. Imai, H. Nakamura, and T. Nanya. : "Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions" 

In Proc. IEEE International Symposium on Asynchronous Circuits and Systems, Vancouver, Canada pp.184-193 2003年  

N. Sretasereekul, H. Saito, M. Imai, E. Kim, M. Ozcan, K. Thongnoo, H. Nakamura, and T. Nanya. : "A Zero-Time-Overhead Asynchronous Four-Phase controller" 

In Proc. IEEE International Symposium on Circuits and Systems, Bangkok, Thailand Vol.5, pp.205-208 2003年  

H. Saito, E. Kim, M. Imai, N. Sretaseereekul, H. Nakamura, and T. Nanya. : "Control Signal Sharing of Asynchronous Circuits Using Datapath Delay Information" 

In Proc. IEEE International Symposium on Circuits and Systems, Bangkok, Thailand Vol.5, pp.617-620 2003年  

H. Saito, S. Kenshu, Y. Kojima, S. Komatsu, and M. Fujita : Engineering Changes in Field Modifiable Architecture 

Proc. ACM/IEEE International Conference on Formal Methods and Models for Codesign 87-94 2003年  

E. Kim, H. Saito, J-G. Lee, D-I. Lee, H. Nakamura, and T. Nanya : Implementation of a Generalized Synchronous Variable Computation Time Arithmetic Unit with a Single-Dual-Single Wrapper 

Proc. International Technical Conference on Circuits/Systems, Computers and Communications 1075-1078 2003年  

N. Sretasereekul, H. Saito, E. Kim, M. Ozcan, M. Imai, H. Nakamura, and T. Nanya : Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design 

IEICE transaction E86-A(12) 3028-3037 2003年  

H. Saito, A. Kondratyev, and T. Nanya : "Design of Asynchronous Controllers with Delay Insensitive Interface" 

In Proc. Asia South Pacific Design Automation Conference, Bangalore, India pp.93-98 2002年  

N. Sretasereekul, Y. Okuyama, H. Saito, M. Imai, K. Kuroda, and T. Nanya. : "Flexible Partitioning of CDFGs for Compact Asynchronous Controllers" 

In Proc. International Technical Conference on Circuits/Systems, Computers and Communications, Phuket, Thai pp.1724-1727 2002年  

Y. Okuyama, N. Sretaserrekul, H. Saito, T. Nanya, and K. Kuroda : Synthesis of Asynchronous Control Circuits Based on Hierarchical CDFG 

IPSJ Journal 43(5) 1225-1234 2002年  

H. Saito, A. Kondratyev, J. Cortadella, L. Lavagno, A. Yakovlev, and T. Nanya : Design of Asynchronous Controllers with Delay Insensitive Interface 

IEICE transaction E85-A(12) 2577-2585 2002年  

H. Saito, A. Kondratyev, J. Cortadella, L. Lavagno, and A. Yakovlev. : "Bridging Modularity and Optimality : Delay-Insensitive Interfacing in Asynchronous Circuits Synthesis" 

In Proc. IEEE International Conference on Systems, Man, and Cybernetics, Tokyo, Japan pp.899-904 1999年  

H. Saito, A. Kondratyev, J. Cortadella, L. Lavagno, and A. Yakovlev. : "What is the Cost of Delay Insensitivity?" 

In Proc. IEEE/ACM International Conference on Computer Aided Design, Sun Jose, CA pp.316-323 1999年