Takashi Matsukawa - My portal

Profile Information

Affiliation: National Institute of Advanced Industrial Science and Technology

Degree: 博士(工学)(早稲田大学)

J-GLOBAL ID: 200901077113076950
researchmap Member ID: 5000086390

External link: http://www.aist.go.jp/RESEARCHERDB/cgi-bin/worker_detail.cgi?call=namae&rw_id=T34207766

Research Areas

Manufacturing technology (mechanical, electrical/electronic, chemical engineering) / Electronic devices and equipment /

Papers

190

Designing a bileg silicon-nanowire thermoelectric generator with cavity-free structure

Md Mehdee Hasan Mahfuz, Motohiro Tomita, Shuhei Hirao, Kazuaki Katayama, Kaito Oda, Takashi Matsukawa, Takeo Matsuki, Takanobu Watanabe

Japanese Journal of Applied Physics, 60(SB) SBBF07-SBBF07, May 1, 2021
4-4 Effect of Unit-cell Arrangement on Performance of Multi-stage-planar Cavity-free Unileg Thermoelectric Generator Using Silicon Nanowires

Katsuki Abe, Kaito Oda, Motohiro Tomita, Takeo Matsuki, Takashi Matsukawa, Takanobu Watanabe

2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sep 23, 2020
Impact of Switching Voltage on Complementary Steep-Slope Tunnel Field Effect Transistor Circuits

Kimihiko Kato, Tetsufumi Tanamoto, Takahiro Mori, Yukinori Morita, Takashi Matsukawa, Mitsuru Takenaka, Shinichi Takagi

IEEE TRANSACTIONS ON ELECTRON DEVICES, 67(9) 3876-3882, Sep, 2020
Effect of the Thermal Boundary Resistance in Metal/Dielectric Thermally Conductive Layers on Power Generation of Silicon Nanowire Microthermoelectric Generators

Tianzhuo Zhan, Shuaizhe Ma, Zhicheng Jin, Hiroki Takezawa, Kohei Mesaki, Motohiro Tomita, Yen-Ju Wu, Yibin Xu, Takashi Matsukawa, Takeo Matsuki, Takanobu Watanabe

ACS Applied Materials & Interfaces, 12(30) 34441-34450, Jul 29, 2020
Source engineering for bilayer tunnel field-effect transistor with hetero tunnel junction: thickness and impurity concentration

Kimihiko Kato, Takahiro Mori, Yukinori Morita, Takashi Matsukawa, Mitsuru Takenaka, Shinichi Takagi

APPLIED PHYSICS EXPRESS, 13(7), Jul, 2020
10μW/cm²-class high power density planar Si-nanowire thermoelectric energy harvester compatible with CMOS-VLSI technology

M. Tomita, S. Oba, Y. Himeda, R. Yamato, K. Shima, T. Kumada, M. Xu, H. Takezawa, K. Mesaki, K. Tsuda, S. Hashimoto, T. Zhan, H. Zhang, Y. Kamakura, Y. Suzuki, H. Inokawa, H. Ikeda, T. Matsukawa, T. Matsuki, T. Watanabe

Digest of Technical Papers - Symposium on VLSI Technology, 2018-June 93-94, Oct 25, 2018
Simulation study of short-channel effects of tunnel field-effect transistors

Koichi Fukuda, Hidehiro Asai, Junichi Hattori, Takahiro Mori, Yukinori Morita, Wataru Mizubayashi, Meishoku Masahara, Shinji Migita, Hiroyuki Ota, Kazuhiro Endo, Takashi Matsukawa

Japanese Journal of Applied Physics, 57(4), Apr 1, 2018 Peer-reviewed
Process and device integration for silicon tunnel FETs utilizing isoelectronic trap technology to enhance the ON current

Takahiro Mori, Hidehiro Asai, Koichi Fukuda, Takashi Matsukawa

Japanese Journal of Applied Physics, 57(4), Apr 1, 2018 Peer-reviewed
Enhancement of capacitance benefit by drain offset structure in tunnel field-effect transistor circuit speed associated with tunneling probability increase

Hidehiro Asai, Takahiro Mori, Takashi Matsukawa, Junichi Hattori, Kazuhiko Endo, Koichi Fukuda

Japanese Journal of Applied Physics, 57(4), Apr 1, 2018 Peer-reviewed
Epitaxial growth of Ge thin film on Si (001) by DC magnetron sputtering

Shintaro Otsuka, Takahiro Mori, Yukinori Morita, Noriyuki Uchida, Yongxun Liu, Shin-ichi O'uchi, Hiroshi Fuketa, Shinji Migita, Meishoku Masahara, Takashi Matsukawa

MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING, 70 3-7, Nov, 2017 Peer-reviewed
Enhanced nickelidation rate in silicon nanowires with interfacial lattice disorder

Shuichiro Hashimoto, Ryo Yokogawa, Shunsuke Oba, Shuhei Asada, Taiyu Xu, Motohiro Tomita, Atsushi Ogura, Takashi Matsukawa, Meishoku Masahara, Takanobu Watanabe

JOURNAL OF APPLIED PHYSICS, 122(14), Oct, 2017 Peer-reviewed
A 0.3-V 1-mu W Super-Regenerative Ultrasound Wake-Up Receiver With Power Scalability

Hiroshi Fuketa, Shinichi O'uchi, Takashi Matsukawa

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 64(9) 1027-1031, Sep, 2017 Peer-reviewed
Anomalous Seebeck coefficient observed in silicon nanowire micro thermoelectric generator

S. Hashimoto, S. Asada, T. Xu, S. Oba, Y. Himeda, R. Yamato, T. Matsukawa, T. Matsuki, T. Watanabe

APPLIED PHYSICS LETTERS, 111(2), Jul, 2017 Peer-reviewed
A Closed-Form Expression for Minimum Operating Voltage of CMOS D Flip-Flop

Hiroshi Fuketa, Shin-ichi O'uchi, Takashi Matsukawa

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 25(7) 2007-2016, Jul, 2017 Peer-reviewed
Impact of residual defects caused by extension ion implantation in FinFETs on parasitic resistance and its fluctuation

Takashi Matsukawa, Yongxun Liu, Takahiro Mori, Yukinori Morita, Shintaro Otsuka, Shin-ichi O'uchi, Hiroshi Fuketa, Shinji Migita, Meishoku Masahara

SOLID-STATE ELECTRONICS, 132 103-108, Jun, 2017 Peer-reviewed
An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

Yongxun Liu, Kazuhiro Koga, Sommawan Khumpuang, Masayoshi Nagao, Takashi Matsukawa, Shiro Hara

Japanese Journal of Applied Physics, 56(6), Jun 1, 2017 Peer-reviewed
Tunnel FinFET CMOS inverter with very low short-circuit current for ultralow-power Internet of Things application

Yukinori Morita, Koichi Fukuda, Yongxun Liu, Takahiro Mori, Wataru Mizubayashi, Shin-ichi O'uchi, Hiroshi Fuketa, Shintaro Otsuka, Shinji Migita, Meishoku Masahara, Kazuhiko Endo, Hiroyuki Ota, Takashi Matsukawa

JAPANESE JOURNAL OF APPLIED PHYSICS, 56(4), Apr, 2017 Peer-reviewed
Suppression of tunneling rate fluctuations in tunnel field-effect transistors by enhancing tunneling probability

Takahiro Mori, Shinji Migita, Koichi Fukuda, Hidehiro Asai, Yukinori Morita, Wataru Mizubayashi, Yongxun Liu, Shin-ichi O'uchi, Hiroshi Fuketa, Shintaro Otsuka, Tetsuji Yasuda, Meishoku Masahara, Hiroyuki Ota, Takashi Matsukawa

JAPANESE JOURNAL OF APPLIED PHYSICS, 56(4), Apr, 2017 Peer-reviewed
Structural and electrical characterization of epitaxial Ge thin films on Si(001) formed by sputtering

Shintaro Otsuka, Takahiro Mori, Yukinori Morita, Noriyuki Uchida, Yongxun Liu, Shin-ichi O'uchi, Hiroshi Fuketa, Shinji Migita, Meishoku Masahara, Takashi Matsukawa

JAPANESE JOURNAL OF APPLIED PHYSICS, 56(4), Apr, 2017 Peer-reviewed
On the drain bias dependence of long-channel silicon-on-insulator-based tunnel field-effect transistors

Koichi Fukuda, Takahiro Mori, Hidehiro Asai, Junichi Hattori, Wataru Mizubayashi, Yukinori Morita, Hiroshi Fuketa, Shinji Migita, Hiroyuki Ota, Meishoku Masahara, Kazuhiko Endo, Takashi Matsukawa

JAPANESE JOURNAL OF APPLIED PHYSICS, 56(4), Apr, 2017 Peer-reviewed

Misc.

SRAM PUF using Polycrystalline Silicon Channel FinFET and Its Evaluation

40(24) 83-87, Aug, 2016
Multigate FinFET Device and Circuit Technology for 10nm and Beyond

MASAHARA Meishoku, ENDO Kazuhiko, OUCHI Shin-ichi, MATSUKAWA Takashi, Liu Yongxun, MIGITA Shinji, MIZUBAYASHI Wataru, MORITA Yukinori, OTA Hiroyuki

Technical report of IEICE. ICD, 114(13) 77-82, Apr 17, 2014
C-3-75 Ultra-Compact Si-Wire 8×8 PILOSS Switch

Suzuki Keijiro, Tanizawa Ken, Matsukawa Takashi, Cong Guangwei, Kim Sang-Hun, Suda Satoshi, Ohno Morifumi, Chiba Tadashi, Tadokoro Hirofumi, Yanagihara Masashi, Igarashi Yasushi, Masahara Meishoku, Namiki Shu, Kawashima Hitoshi

Proceedings of the IEICE General Conference, 2014(1) 230-230, Mar 4, 2014
A Study on 1/f Noise Characteristic in Independent-Double-Gate-FinFET

Sakai Hideo, O'uchi Shin-ichi, Endo Kazuhiko, Matsukawa Takashi, Liu Yongxun, Ishikawa Yuki, Tsukada Junichi, Nakagawa Tadashi, Sekigawa Toshihiro, Koike Hanpei, Masahara Meishoku, Ishikuro Hiroki

Technical report of IEICE. ICD, 113(112) 119-124, Jul 4, 2013
CT-2-5 Device Technology for a Low Voltage SRAM

O'uchi S., Endo K., Matsukawa T., Liu Y. X., Nakagawa T., Ota H., Morita Y., Migita S., Mizubayashi W., Ishikawa Y., Tsukada J., Yamauchi H., Sekigawa T., Koike H., Sakamoto K., Masahara M.

Proceedings of the Society Conference of IEICE, 2012(2) "SS-21"-"SS-24", Aug 28, 2012
Experimental study of effective carrier mobility of multi-fin-type double-gate metal-oxide-semiconductor field-effect transistors with (111) channel surface fabricated by orientation-dependent wet etching

YX Liu, E Sugimata, K Ishii, M Masahara, K Endo, T Matsukawa, H Yamauchi, S O'uchi, E Suzuki

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 45(4B) 3084-3087, Apr, 2006
Fabrication of a vertical-channel double-gate metal-oxide-semiconductor field-effect transistor using a neutral beam etching

K Endo, S Noda, M Masahara, T Kubota, T Ozaki, SJ Samukawa, YX Liu, K Ishii, Y Ishikawa, E Sugimata, T Matsukawa, H Takashinia, H Yamauchi, E Suzuki

JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, 45(8-11) L279-L281, Mar, 2006
Fabrication and characterization of vertical-type double-gate metal-oxide-semiconductor field-effect transistor with ultrathin Si channel and self-aligned source and drain

M Masahara, YX Liu, K Endo, T Matsukawa, K Sakamoto, K Ishii, S O'uchi, E Sugimata, H Yamauchi, E Suzuki

APPLIED PHYSICS LETTERS, 88(7) 0721031-0721033, Feb, 2006
Vertical ultrathin-channel multi-gate MOSFETs (MuGFETs):Technological challenges and future developments

IEEJ Transactions on Electrical and Electronics Engineering, 2006
縦型ダブルゲートMOSFETデバイス技術

電気学会誌, 2006
Demonstration and analysis of accumulation-modeDG=MOSFET

JJAP, 2006
Doping integrity diagnostics of planar transistor channel structures by scanning nonlinear dielectric microscopy

T Matsukawa, M Masahara, H Tanoue, S Kanemaru, E Suzuki

JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 24(1) 237-244, Jan, 2006
A New Fabrication Technology of FinFETs using a Neutral Beam Etching

JAPANESE JOURNAL OF APPLIED PHYSICS, 45(6B) 5513-5516, 2006
Investigation of N-Channel Triple-Gate MOSFETs on (100) SOI Substrate

JAPANESE JOURNAL OF APPLIED PHYSICS, 45(4B) 3097-3100, 2006
Demonstration, analysis, and device design considerations for independent DG MOSFETs

M Masahara, YX Liu, K Sakamoto, K Endo, T Matsukawa, K Ishii, T Sekigawa, H Yamauchi, H Tanoue, S Kanemaru, H Koike, E Suzuki

IEEE TRANSACTIONS ON ELECTRON DEVICES, 52(9) 2046-2053, Sep, 2005
Fabrication of HfC-coated Si field emitter arrays with built-in poly-Si thin-film transistor

M Nagao, Y Sacho, T Matsukawa, S Kanemaru, J Itoh

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 44(7B) 5740-5743, Jul, 2005
Work function controllability of metal gates made by interdiffusing metal stacks with low and high work functions

T Matsukawa, YX Liu, A Masahara, K Ishii, K Endo, H Yamauchi, E Sugimata, H Takashima, T Higashino, E Suzuki, S Kanemaru

MICROELECTRONIC ENGINEERING, 80 284-287, Jun, 2005
Demonstration of dopant profiling in ultrathin channels of vertical-type double-gate metal-oxide-semiconductor field-effect-transistor by scanning nonlinear dielectric microscopy

M Masahara, S Hosokawa, T Matsukawa, K Endo, Y Naitou, H Tanoue, E Suzuki

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 44(4B) 2400-2404, Apr, 2005
Scanning tunneling microscopy observations of hafnium carbide thin films as a field emission material

T Sato, M Saida, K Horikawa, M Sasaki, M Nagao, S Kanemaru, T Matsukawa, J Itoh, S Yamamoto

JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 23(2) 741-744, Mar, 2005
Work function uniformity of Al-Ni alloys obtained by scanning Maxwell-stress microscopy as an effective tool for evaluating metal transistor gates

T Matsukawa, C Yasumuro, H Yamauchi, M Masahara, E Suzuki, S Kanemaru

APPLIED PHYSICS LETTERS, 86(9) 094104-1-094104-3, Feb, 2005