2018年4月1日
Process and device integration for silicon tunnel FETs utilizing isoelectronic trap technology to enhance the ON current
Japanese Journal of Applied Physics
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- 巻
- 57
- 号
- 4
- 記述言語
- 英語
- 掲載種別
- 研究論文(国際会議プロシーディングス)
- DOI
- 10.7567/JJAP.57.04FA04
- 出版者・発行元
- Japan Society of Applied Physics
A tunnel FET (TFET) is a candidate replacement for conventional MOSFETs to realize low-power LSI. The most significant issue with the practical application of TFETs concerns their low tunneling current. Si is an indirect-gap material with a low band-to-band tunneling probability and is not favored for the channel. However, a new technology has recently been proposed to enhance the tunneling current in Si-TFETs by utilizing isoelectronic trap (IET) technology. IET technology provides an innovative approach to realizing low-power LSI with TFETs. In this paper, state-of-the-art research on Si-TFETs with IET technology from the viewpoint of process and device integration is reviewed.
- リンク情報
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- DOI
- https://doi.org/10.7567/JJAP.57.04FA04
- Web of Science
- https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:000430981800005&DestApp=WOS_CPL
- URL
- http://orcid.org/0000-0003-0106-6485
- Scopus
- https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85044469101&origin=inward
- Scopus Citedby
- https://www.scopus.com/inward/citedby.uri?partnerID=HzOxMe3b&scp=85044469101&origin=inward
- ID情報
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- DOI : 10.7567/JJAP.57.04FA04
- ISSN : 1347-4065
- ISSN : 0021-4922
- eISSN : 1347-4065
- ORCIDのPut Code : 45262832
- SCOPUS ID : 85044469101
- Web of Science ID : WOS:000430981800005