WADA Yasutaka

J-GLOBAL         Last updated: Jul 18, 2019 at 02:46
 
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Name
WADA Yasutaka
Affiliation
Meisei University
Section
School of Information Science, Department of Information Science
Degree
Bachelor of Engineering(Waseda University), Master of Engineering(Waseda University), Doctor of Engineering(Waseda University)

Research Areas

 
 

Academic & Professional Experience

 
Apr 2006
 - 
Mar 2009
Waseda University School of Science and Engineering Research Assistant
 
Apr 2009
 - 
Mar 2010
Waseda University Information Technology Research Organization Junior Researcher
 
Apr 2010
 - 
Mar 2012
Waseda University Graduate School of Fundamental Science and Engineering Assistant Professor
 
Sep 2010
 - 
Mar 2012
Egypt-Japan University of Science and Technology Department of Computer Science and Engineering Associate Professor
 
Apr 2012
 - 
Aug 2014
The University of Elector-Communications Graduate School of Information Systems Assistant Professor
 

Education

 
Apr 1998
 - 
Mar 2002
Department of Electrical, Electronics and Computer Engineering, Faculty of Science and Engineering, Waseda University
 
Apr 2002
 - 
Mar 2004
Major in Electrical Engineering, Graduate School of Science and Engineering, Waseda University
 
Apr 2004
 - 
Mar 2007
Major in Computer Science, Graduate School of Science and Engineering, Waseda University
 

Committee Memberships

 
Apr 2012
 - 
Mar 2016
Information Processing Society of Japan
 
May 2012
 - 
Apr 2018
The Institute of Electronics, Information and Communication Engineers of Japan
 
Apr 2015
 - 
Mar 2019
Information Processing Society of Japan
 
Sep 2015
 - 
Today
Information Processing Society of Japan
 
Nov 2015
 - 
Today
The Institute of Electronics, Information and Communication Engineers of Japan
 

Published Papers

 
Daisuke Ogawa, Yoichi Sato, Yasutaka Wada, and Kanji Otsuka
Transactions of The Japan Institute of Electronics Packaging   12 E18-008-1-E18-008-7   Jun 2019   [Refereed]
This paper is the progressive study of previous papers presented at the IMPACT 2015 and ICEP 2018, and evaluates effectiveness and applicability of MLCS (Memory Logic Conjugated System) with a simple deep learning processing. NVIDIA, Google, Fujit...
Ghada Abozaid, Arnaud Tisserand, Ahmed El-Mahdy, and Yasutaka Wada
IEEE Embedded Systems Letters      Jun 2015   [Refereed]
Sameh Samra, Ahmed El-Mahdy, and Yasutaka Wada
Transactions on Intelligent Transportation Systems   16(1) 387-395   Feb 2015   [Refereed]
Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, and Hironori Kasahara
Transactions on High-Performance Embedded Architectures and Compilers IV   215-233   Nov 2011   [Refereed]
A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core
Osamu NISHII, Yoichi YUYAMA, Masayuki ITO, Yoshikazu KIYOSHIGE, Yusuke NITTA, Makoto ISHIKAWA, Tetsuya YAMADA, Junichi MIYAKOSHI, Yasutaka WADA, Keiji KIMURA, Hironori KASAHARA, and Hideo MAEJIMA
IEICE TRANSACTIONS on Electronics   E94-C(4) 663-669   Apr 2011   [Refereed]

Conference Activities & Talks

 
Simple DSL for Power-Performance Modeling with Segmented Linear Models
Yuan He, Yasutaka Wada, Guanqin Pan, Masaaki Kondo
48th International Conference on Parallel Processing (ICPP2019)   6 Aug 2019   
An FPGA based Autonomous Driving Car Design using Multiple Simple Neural Networks for Decision Making
Aoto Musashi, Shoya Hirukawa, Yasutaka Wada, and Kazutaka Maruyama
Autonomous Vehicle Driving Competition using FPGA, The 10th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART2019)   Jun 2019   
Software-Based Resource Management Techniques for Computer Systems of Various Scales [Invited]
Yasutaka Wada
International Conference on Soft Computingand Machine Learning (SCML2019)   28 Apr 2019   
Development of an FPGA controlled "Mini-Car" toward Autonomous Driving
Musashi Aoto, Yousuke Numata, and Yasutaka Wada
FPGA Design Competition, The 2018 International Conference on Field-Programmable Technology (FPT'18)   12 Dec 2018   
Accelerating Deep Learning Training with MLCS (Memory Logic Conjugated System)
Daisuke Ogawa, Yasutaka Wada, Kanji Otsuka, Yoichi Sato
International Colloquium of Mexican & Japanese Studies   17 Oct 2018   University Program of Studies on Asia and Africa, National Autonomous University of Mexico

Works

 
Multigrain parallel processing on compiler cooperative chip multiprocessor
Keiji Kimura, Yasutaka Wada, Hirofumi Nakano, Takeshi Kodaka, Jun Shirako, Kazuhisa Ishizaka, and Hironori Kasahara   The Others   Feb 2005
Compiler Control Power Saving Scheme for Multi Core Processors
Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, and Hironori Kasahara   The Others   Oct 2005
Parallelizing Compilation Scheme for Reduction of Power Consumption of Chip Multiprocessors
Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, and Hironori Kasahara   The Others   Jan 2006
Performance Evaluation of Heterogeneous Chip Multi-Processor with MP3 Audio Encoder
Hiroaki Shikano, Yuki Suzuki, Yasutaka Wada, Jun Shirako, Keiji Kimura, and Hironori Kasahara   The Others   Apr 2006
Performance Evaluation of Compiler Controlled Power Saving Scheme
J. Shirako, M. Yoshida, N. Oshiyama, Y. Wada, H. Nakano, H. Shikano, K. Kimura, and H. Kasahara   The Others   Jul 2006

Research Grants & Projects

 
The Japan Society for the Promotion of Science: Challenging Research (Exploratory)
Project Year: Jun 2018 - Mar 2020
The Japan Society for the Promotion of Science: Grant-in-Aid for Young Scientists (B)
Project Year: Apr 2017 - Mar 2020
The Japan Society for the Promotion of Science: Grant-in-Aid for Young Scientists (B)
Project Year: Apr 2012 - Mar 2015

Patents

 
US8250548 : Method for controlling heterogeneous multiprocessor and multigrain parallelizing compiler
Hironori Kasahara, Keiji Kimura, Jun Shirako, Yasutaka Wada, Masaki Ito, Hiroaki Shikano